Clock Relationship Re-convergence Analysis for IC Design
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Solution Overview
Problem
Current clock domain cross verification tools fail to accurately identify re-convergence issues in integrated circuits due to incomplete consideration of clock relationships among multiple synchronizers, leading to potential functional failures and false noise violations.
Innovation Solution
A method that generates a levelized topological abstract graph (LTAG) to identify and analyze clock domain crossing (CDC) synchronizers, traverses the graph to detect converging points, and suppresses noisy violations by considering synchronous and asynchronous clock relationships, thereby flagging only valid coherency issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional clock domain cross verification tools are used to identify re-convergence issues, then verification coverage is limited, but false noise violations increase and measurement precision deteriorates
Solution Approach 1:
The verification process is segmented into distinct phases: initial re-convergence analysis to identify potential violations, followed by clock relationship-based filtering to eliminate false positives. This segmentation allows the tool to maintain high detection sensitivity while reducing false noise through systematic filtering of identified violations.
2Measurement precision
If comprehensive clock relationship analysis is performed on all synchronizers, then measurement precision improves, but device complexity and processing overhead increase
Solution Approach 1:
Clock relationship analysis is performed preliminarily on CDC synchronizers before detailed re-convergence verification. By pre-characterizing clock relationships and organizing synchronizers into groups based on their clock domains, the verification process can focus computational resources only on critical paths, reducing overall complexity while maintaining detection precision.
3Measurement precision
If detailed analysis of all CDC synchronizers is performed, then detection precision improves, but processing time and resource consumption increase
Solution Approach 1:
The verification tool applies different analysis depths to different regions of the design based on local characteristics. CDC synchronizers with critical clock relationships receive detailed analysis, while those in non-critical paths undergo simplified verification. This localized quality approach maintains high detection precision for critical issues while reducing overall processing time.
Data Source
AI summary
A clock relationship based re-convergence analysis method includes receiving, by a processing device, a register-transfer level (RTL) description of a design relating to an integrated circuit (IC). The method further includes identifying one or more clock domain crossing (CDC) synchronizers in the RTL description of the design, and generating a levelized topological abstract graph (LTAG) including a network of nodes. Each node includes a CDC synchronizer. The method further includes traversing the LTAG starting from a first output of the one or more CDC synchronizers, and responsive to determining that a first CDC synchronizer of the one or more CDC synchronizers is converging with a second CDC synchronizer, identifying a first potential convergence violation associated with the first CDC synchronizer and the second CDC synchronizer.