Digital Clock Recovery Circuit Using 8UI Voting Pulses
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Solution Overview
Problem
High-speed serial links face challenges in clock and data recovery due to increased power and silicon area requirements, with existing CDR circuits experiencing issues in maintaining accurate timing recovery and bit error rate, especially in low-end CMOS technologies where 2UI pulses result in incomplete settling and pattern-dependent proportional gain.
Innovation Solution
A digital clock data recovery circuit with a layered structure, utilizing multiple deserializers, vote circuits, and digital-to-analog converters to generate and control voltage and frequency of a voltage-controlled oscillator, employing 8UI wide pulses and majority voting to ensure complete settling and robust proportional path control, thereby improving CDR stability and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 2UI pulses are used in CDR circuits, then the circuit structure is simpler, but incomplete settling occurs in low-end CMOS technologies leading to pattern-dependent proportional gain
Solution Approach 1:
The patent changes the pulse width parameter from 2UI to 8UI to ensure complete settling in low-end CMOS technologies. This parameter change eliminates pattern-dependent proportional gain while maintaining circuit structure simplicity, directly resolving the contradiction between device complexity and reliability.
2Productivity
If interface speed increases to handle increased data transmission, then data transmission capacity improves, but power and silicon area of the communication receiver increase
Solution Approach 1:
The patent segments the proportional path control into multiple independent paths (first proportional path with first DAC, second proportional path with second DAC). This segmentation allows parallel processing of even and odd pulses, improving data transmission capacity while distributing power consumption across multiple smaller components rather than one large consumer.
3Productivity
If interface speed increases to handle increased data transmission, then data transmission capacity improves, but silicon area of the communication receiver increases
Solution Approach 1:
The patent merges the control inputs of both DACs to the same VCO. This merging allows two separate proportional paths to share a common output stage, effectively reducing the silicon area that would be required if separate VCOs were used for each path, thus resolving the contradiction between productivity and area.
4Reliability
If multiple proportional path controls are implemented, then CDR stability and bandwidth improve, but device complexity increases
Solution Approach 1:
The patent introduces a layered architecture where digital vote circuits process pulses in the digital domain before analog conversion. This adds a temporal dimension to the control process, allowing complex stabilization functions to be achieved through time-multiplexed digital logic rather than complex analog circuitry, thus improving CDR stability while managing device complexity.
Data Source
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AI summary
A digital clock data recovery circuit (100) including: a first vote circuit (430) connected at an output of a first deserializer (410) and configured to generate an even up/down signal based on even deserialized signals from the first deserializer (410); a first DAC (451) connected at an output of the first vote circuit (420) and configured to control a voltage and/or frequency of a voltage controlled oscillator, VCO, (460) based on the even up/down signal from the first vote circuit (420); a second vote circuit (440) connected at an output of a second deserializer (430) and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer (430); and a second DAC (452) connected at an output of the second vote circuit (440) and configured to control the voltage and/or frequency of the VCO (460) based on the odd up/down signal from the second vote circuit (440).