Clock Recovery Loop with Adaptive Packet Filtering for PDV Noise

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Solution Overview

Problem

Conventional packet-based communication systems face sub-optimal frequency synchronization due to packet delay variation (PDV) noise, particularly under varying traffic patterns, where sample-minimum filtering is not effective in all network conditions.

Innovation Solution

A clock recovery loop with a phase error estimator that adaptively selects from multiple packet filters based on variance measures to minimize phase noise, incorporating filters like sample-minimum, sample-maximum, and sample-mean filters to generate master clock phase estimates from timestamps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If sample-minimum filtering is used to filter packet delay variation noise, then filtering effectiveness is improved under certain network conditions, but filtering performance deteriorates under other traffic patterns and network conditions

Engineering Contradiction:
Improvephase error estimation accuracyVSAvoidfiltering effectiveness across different network conditions
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The system dynamically adapts the filtering approach by selecting from multiple filter types (sample-minimum, sample-maximum, sample-mean) based on real-time network conditions. The slave device monitors packet delay characteristics and adjusts the filtering method accordingly, transforming a static filtering system into a dynamic one that responds to changing network environments.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the filtering parameter (filter type selection) based on measured network conditions. By calculating packet delay variation and comparing it against thresholds, the system selects appropriate filter characteristics to optimize phase error estimation for current network states, thereby resolving the contradiction between precision and adaptability.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If multiple packet filters are maintained for different network conditions, then adaptability to varying traffic patterns is improved, but device complexity increases

Engineering Contradiction:
Improvefilter selection capabilityVSAvoidclock recovery module complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The filtering function is segmented into multiple specialized filters (sample-minimum, sample-maximum, sample-mean), each optimized for specific network conditions. Rather than one complex adaptive filter, the system uses several simpler filters that can be selectively applied, reducing overall system complexity while maintaining adaptability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements self-service through automated filter selection based on measured network conditions. The slave device autonomously monitors packet delays, determines appropriate filter types, and applies them without external intervention, managing the complexity internally while presenting a simple interface for frequency synchronization.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8693608B2Frequency synchronization using clock recovery loop with adaptive packet filtering
Publication Date: 2014.04.08 WSOU INVESTMENTS LLC
  • US8693608B2 patent drawing
  • US8693608B2 patent drawing
  • US8693608B2 patent drawing

AI summary

An endpoint or other communication device of a communication system includes a clock recovery loop having a phase error estimator. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery loop is configured to control a slave clock of the slave device responsive to a phase error estimate generated by the phase error estimator so as to synchronize the slave clock with a master clock of the master device. The phase error estimator comprises a plurality of filters each configured to generate a different estimate of master clock phase using at least a subset of a plurality of packets received from the master device, and control logic for adaptively selecting at least a particular one of the plurality of filters for use in generating the phase error estimate to be processed in the clock recovery loop.