Clock Recovery Circuit With Adaptive Jitter Control Across Frequency Bands
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Solution Overview
Problem
High resolution display devices face challenges in maintaining jitter characteristics of clock signals across a wide frequency band, leading to errors in data recovery due to optimization for high-speed operation regions, which is not suitable for low-speed regions.
Innovation Solution
A clock and data recovery circuit that includes an automatic frequency controller, voltage-controlled oscillator, charge pump, and loop filter, which detects the frequency band of the reference clock signal and adjusts parameters to maintain jitter characteristics across a wide frequency range, ensuring stable clock signal recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock and data recovery circuit is optimized for high-speed operation region, then high-speed performance is improved, but jitter characteristics deteriorate in low-speed operation region
Solution Approach 1:
The patent implements dynamic parameter adjustment in the phase locked loop circuit based on the operating frequency band. The controller detects whether the input signal is in high-speed or low-speed region and automatically adjusts the loop filter parameters and charge pump current accordingly. This dynamic adaptation allows the circuit to maintain optimal jitter characteristics across both high-speed and low-speed operation regions, resolving the contradiction between high-speed performance and low-speed reliability
Solution Approach 2:
The patent changes physical parameters of the phase locked loop circuit based on the operating frequency band. Specifically, the loop filter's resistance and capacitance values are adjusted, and the charge pump's output current is modified depending on whether the circuit operates in high-speed or low-speed region. These parameter changes enable the circuit to optimize its performance for each operating condition, preventing jitter degradation in either region
2Device complexity
If a single parameter configuration is used for the phase locked loop circuit, then device complexity is reduced, but operational stability across wide frequency band deteriorates
Solution Approach 1:
The patent introduces dynamic parameter adjustment mechanisms that automatically adapt the phase locked loop circuit's characteristics based on the detected frequency band. The controller monitors the input signal frequency and switches between different parameter sets (loop filter values, charge pump current) to maintain stability across the wide frequency band, achieving both simplicity and reliability through automated adaptation rather than manual configuration
Solution Approach 2:
The patent segments the operating frequency band into distinct regions (high-speed and low-speed) and applies different parameter configurations for each segment. This segmentation allows the circuit to be optimized for specific frequency ranges while maintaining overall stability across the entire operating band, balancing complexity and reliability by treating different operating conditions as separate manageable segments
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows the clock and data recovery circuit to operate stably across a wide frequency band, reducing jitter and maintaining optimal performance in both high-speed and low-speed operation regions, thereby enhancing the display device's operational efficiency.
Implementation Method 1
a voltage-controlled oscillator for outputting a second internal clock signal according to the frequency band, and outputting a third internal clock signal based on a control voltage
Implementation Method 2
a charge pump for determining a current to be output in response to a phase control signal corresponding to a phase difference between the reference clock signal and the second internal clock signal
Data Source
AI summary
A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.