Clock Recovery Circuit With Auxiliary Path for Low Loop Latency
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Solution Overview
Problem
Conventional digital-based clock and data recovery (CDR) circuits suffer from long loop latency due to speed limitations in semiconductor processes, making them unsuitable for high-speed applications.
Innovation Solution
A CDR circuit design incorporating a first phase detector, controller, and phase filter with a second path utilizing an auxiliary signal to reduce overall latency, where the phase detector generates a control signal and an auxiliary signal to adjust the clock signal, effectively mitigating the long loop latency issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional digital controller is used in the CDR circuit, then the circuit structure is simple and easy to manufacture, but the loop latency becomes long due to speed limitations in semiconductor processes
Solution Approach 1:
The CDR circuit is divided into two parallel paths: a first path containing a digital controller for general control functions, and a second path containing an auxiliary signal generation unit for rapid phase adjustment. This segmentation allows each path to be optimized for its specific function, reducing overall loop latency while maintaining manufacturing simplicity.
Solution Approach 2:
The auxiliary signal is generated in advance based on the phase detection result, before the digital controller completes its full processing cycle. This preliminary action enables the phase filter to receive advance notice of phase errors and begin correction faster, reducing loop latency without complicating the overall circuit structure.
2Loss of time
If the CDR circuit is designed for high-speed applications, then the loop latency must be reduced, but this increases the circuit complexity and manufacturing difficulty
Solution Approach 1:
The phase filter serves as an intermediary component that receives inputs from both the digital controller (first path) and the auxiliary signal generation unit (second path). It combines the control signal and auxiliary signal to generate the final clock signal, allowing fast response without requiring complete redesign of the entire CDR circuit.
Solution Approach 2:
The auxiliary signal provides an additional, redundant control path that operates in parallel with the main digital controller. This partial action approach adds only the necessary components for speed improvement without over-engineering the entire system, balancing complexity reduction with latency improvement.
3Device complexity
If a single control path is used in the CDR circuit, then the circuit structure is simple, but the overall latency cannot be reduced sufficiently for high-speed applications
Solution Approach 1:
The invention adds a temporal dimension to the control architecture by creating two parallel time paths: a longer first path through the digital controller and a shorter second path through the auxiliary signal generation. This dimensional change in signal processing architecture enables faster response without increasing spatial complexity of individual components.
Data Source
AI summary
The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.