Clock Recovery Circuit with Auxiliary Phase Tracking

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Solution Overview

Problem

High-speed integrated circuits face challenges in maintaining lock on clock and data signals due to prolonged periods of data signal stability, leading to potential loss of lock in communication systems.

Innovation Solution

A clock and data recovery circuit incorporating a first phase detector, an auxiliary module with an auxiliary clock generator and phase detector, a multiplexing selecting unit, and a voltage-controlled oscillator, which generates and adjusts the clock signal frequency based on phase comparisons to prevent lock loss during prolonged data signal stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the clock and data recovery circuit relies on data signal transitions for phase/frequency tracking, then the circuit can operate correctly during normal data transmission, but the circuit will lose lock when the data signal remains stable for a long period

Engineering Contradiction:
Improvelock maintenance capabilityVSAvoidresponse to different data signal conditions
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The auxiliary clock generator pre-generates an auxiliary clock signal that is independent of data signal transitions. This preliminary action ensures that when data signal transitions are absent, the phase detector still has a valid reference signal to maintain lock, preventing the loss of lock condition that would otherwise occur during prolonged data stability periods

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The auxiliary clock signal acts as an intermediary between the existing phase detector and the VCO. When data transitions are present, the normal data-to-phase-detector path is used. When data transitions are absent, the auxiliary clock signal intermediates by providing an alternative reference to the phase detector, ensuring continuous lock maintenance without disrupting the normal operation path

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the circuit uses a single phase detector for phase tracking, then the circuit structure remains simple, but the circuit cannot maintain lock during prolonged periods of data signal stability

Engineering Contradiction:
Improvecontinuous lock capabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The auxiliary clock generator and multiplexing selecting unit create a multi-functional phase detection system. The same phase detector structure serves dual purposes: it processes normal data signal transitions during active communication and processes auxiliary clock signals during prolonged stability periods. This universality allows the circuit to maintain reliability across different operating conditions without proportionally increasing overall circuit complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention merges the normal data signal processing path with the auxiliary clock signal path through the multiplexing selecting unit. Both paths feed into the same phase detector and charge pump structure, combining their functions into a unified system. This merging allows the circuit to switch between operating modes while sharing common components, thereby improving reliability without linearly increasing device complexity

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10615804B2Clock and data recovery circuit
Publication Date: 2020.04.07 MEDIATEK INC
  • US10615804B2 patent drawing
  • US10615804B2 patent drawing
  • US10615804B2 patent drawing

AI summary

A clock and data recovery circuit includes a first phase detector, a first charge pump, a first voltage-controlled oscillator (VCO), and an auxiliary module. The auxiliary module includes: an auxiliary clock generator, generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, comparing a phase of the auxiliary clock signal with that of a first clock signal outputted by the first VCO; and a multiplexing selecting unit, outputting a multiplexing output signal to the first charge pump according to a selection signal.