Clock Recovery Loop Bandwidth Control for Jitter and Settling Time
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Solution Overview
Problem
Conventional clock and data recovery circuits face a trade-off between settling time and jitter due to a fixed loop bandwidth, which is inadequate for dynamically changing input data frequencies, leading to suboptimal performance.
Innovation Solution
A clock and data recovery circuit with a controller that dynamically adjusts loop bandwidth by determining the run length of input data and controlling the voltage controlled oscillator, loop filter, and charge pump unit to optimize bandwidth based on input data frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If loop bandwidth is set to 1/10 of the highest frequency of input data, then stability is improved, but jitter of output clock becomes large when frequency of input data becomes low
Solution Approach 1:
The patent implements dynamic loop bandwidth adjustment by detecting input data frequency and automatically adapting the loop bandwidth parameter. When input frequency is high, loop bandwidth is set to 1/10 of input frequency for stability; when input frequency is low, loop bandwidth is increased to reduce jitter. This dynamic adaptation resolves the contradiction between stability and jitter across different operating conditions.
Solution Approach 2:
The patent changes the loop bandwidth parameter based on detected input data frequency characteristics. By monitoring frequency transitions and adjusting the loop bandwidth parameter accordingly (increasing it when frequency decreases, decreasing it when frequency increases), the system optimizes both stability and jitter performance for different input conditions.
2Manufacturing precision
If loop bandwidth is set to 1/10 of the lowest frequency of input data, then jitter is reduced, but tracking speed becomes slow when frequency of input data becomes high, resulting in longer settling time
Solution Approach 1:
The system dynamically adjusts loop bandwidth based on real-time frequency detection. When input frequency is high, loop bandwidth is reduced to increase tracking speed and decrease settling time. When input frequency is low, loop bandwidth is increased to reduce jitter. This dynamic parameter adjustment resolves the contradiction between jitter reduction and tracking speed.
Solution Approach 2:
The patent implements parameter change by adjusting loop bandwidth according to detected frequency transitions. The system monitors frequency changes and modifies the loop bandwidth parameter to optimize tracking performance at high frequencies while maintaining low jitter at low frequencies, thereby resolving the speed-jitter trade-off.
3Device complexity
If loop bandwidth is fixed, then circuit design is simplified, but there is a trade-off between settling time and jitter performance
Solution Approach 1:
The patent introduces dynamic loop bandwidth adjustment with frequency detection and automatic parameter adaptation. Although this increases circuit complexity compared to a fixed bandwidth design, it eliminates the performance trade-off between settling time and jitter by optimizing loop bandwidth for each operating condition, achieving superior overall performance.
Data Source
AI summary
A clock and data recovery circuit includes a voltage controlled oscillator for generating an output clock according to a control voltage signal, a loop filter for outputting the control voltage signal according to a current output, a charge pump unit for outputting the current output according to an error signal, and a controller for determining a run length corresponding to input data based on the output clock from the voltage controlled oscillator. The controller further controls at least one of the voltage controlled oscillator, the loop filter and the charge pump unit according to the run length to dynamically adjust loop bandwidth. A method of adjusting loop bandwidth is also disclosed.