Clock Data Recovery Circuit with Restoration Hold for Bang-Bang Errors

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Solution Overview

Problem

Bang-bang errors occur in feedback-based integrated circuits due to the time taken for comparison results to be incorporated into feedback signals, affecting the accuracy of these circuits.

Innovation Solution

Incorporating a restoration signal generation unit that enables a restoration signal when the up/down signal maintains an identical value for a specific time and changes, allowing the processing circuit to hold or restore process results, thereby reducing errors by adjusting the feedback signal generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the processing circuit processes the up/down signal sequentially through multiple stages, then the feedback signal is generated based on accumulated processing results, but this causes time delay in incorporating comparison results into the feedback signal, leading to bang-bang errors

Engineering Contradiction:
Improveaccuracy of feedback signalVSAvoidtime delay in feedback incorporation
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by detecting when the up/down signal maintains an identical value for a predetermined time period and proactively generating a restoration signal before the bang-bang error fully develops. This allows the system to preemptively correct the feedback signal by restoring previous processing results, thereby reducing the time delay effect and improving measurement precision without requiring longer processing sequences

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the restoration signal is generated when the up/down signal maintains an identical value for a specific time, then bang-bang errors are reduced, but this requires additional monitoring and control logic in the processing circuit

Engineering Contradiction:
Improvereduction of bang-bang errorsVSAvoidcomplexity of processing circuit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback by continuously monitoring the up/down signal states and using this information to control the restoration signal generation. The processing circuit uses the monitored signal patterns to feedback-control when to restore previous results, achieving reliable error reduction through a systematic feedback mechanism that, while adding some complexity, provides automated error correction without requiring overly complex external control logic

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9667261B2Integrated circuit and clock data recovery circuit
Publication Date: 2017.05.30 SK HYNIX INC
  • US9667261B2 patent drawing
  • US9667261B2 patent drawing
  • US9667261B2 patent drawing

AI summary

An integrated circuit includes a comparator capable of generating an up/down signal by comparing a feedback signal with a reference signal; a restoration signal generation unit capable of enabling a restoration signal when the up/down signal maintains an identical value for greater than or equal to a first specific time and changes afterwards; a processing circuit including one or more stages for sequentially processing the up/down signal, wherein a last one of the one or more stages holds a process result thereof for a second specific time when the restoration signal is enabled; and a feedback unit capable of generating the feedback signal in response to the process result of the last stage.