Clock Recovery Circuit With Bias-Controlled Phase Fine-Tuning
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits struggle to fine-tune the phase of the recovery clock to achieve optimal eye width and height, especially without decision feedback equalizer (DFE), and even with DFE, the phase is not necessarily in the best position.
Innovation Solution
A clock and data recovery circuit that adjusts phase using positive and negative bias voltages through edge sampling and phase error detection, incorporating multiple equalization modules and sampling modules to generate and adjust sampling data, allowing for precise phase adjustment and clock recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase detection is performed using conventional phase detectors, then phase information can be extracted, but the phase cannot be fine-tuned to achieve optimal eye width and height
Solution Approach 1:
The patent changes the parameter of bias voltage applied to the sampling circuit to achieve phase fine-tuning. By adjusting the bias voltage, the sampling point phase can be precisely controlled to achieve optimal eye width and height, resolving the contradiction between phase detection capability and phase adjustment precision.
2Reliability
If decision feedback equalizer (DFE) is used to control phase, then equalization is improved, but the phase is not necessarily in the best position
Solution Approach 1:
The patent introduces an intermediary mechanism - the bias voltage controlled sampling circuit - that acts between the DFE equalization process and the final phase determination. This intermediary allows independent optimization of both equalization performance and phase position accuracy by providing an additional control degree of freedom through bias voltage adjustment.
3Adaptability or versatility
If multiple sampling modules with bias voltage are added, then phase adjustment capability is improved, but device complexity increases
Solution Approach 1:
The patent makes the sampling circuit multi-functional by enabling it to perform both normal sampling and phase fine-tuning functions. The same sampling circuit structure can operate in different modes: standard phase-locked sampling and bias-voltage-controlled fine-tuning sampling, thereby improving adaptability without proportionally increasing complexity.
Data Source
AI summary
Disclosed are a clock and data recovery circuit, method and apparatus. The circuit comprises a receiving module for receiving an analog signal; a first equalization module connected to the receiving module, the first equalization module comprising a first totalizer and a second totalizer; a first sampling module connected to an output end of the first totalizer, the first sampling module comprising a first edge sampler and a second edge sampler that are connected to the output end of the first totalizer, respectively; a second sampling module connected to an output end of the second totalizer; a data processing module connected to both the first sampling module and the second sampling module; a clock recovery module connected to the data processing module; and an output module connected to the clock recovery module. In the present application, by means of the manner, a phase can be adjusted using a bias voltage, thereby accurately recovering clock information.