Clock Recovery Circuit With Capacitive Voting for Jitter Tolerance
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Solution Overview
Problem
Conventional clock and data recovery circuits in high-speed serial transmission have reduced jitter tolerance due to increased response time, which affects their data receiving capability.
Innovation Solution
A clock and data recovery circuit comprising a phase detection circuit, a first voting circuit, a low-pass filtering circuit, and a phase interpolation circuit, where the phase detection circuit generates a phase signal, the voting circuit charges capacitance components based on this signal to produce a voting signal, and the low-pass filtering circuit generates a phase control signal to adjust the clock signal, thereby improving the circuit's efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the voting circuit samples the data signal for multiple cycles, then the statistical accuracy is improved, but the response time increases
Solution Approach 1:
The patent pre-charges capacitance components during idle periods or stable phases before actual voting operations begin. This preliminary charging action ensures that when multiple-cycle sampling is required for statistical accuracy, the circuit is already in an optimal state, reducing the effective response time penalty while maintaining measurement precision.
Solution Approach 2:
The patent implements continuous charging of capacitance components throughout the operation, rather than intermittent charging. This continuous action ensures that the voting circuit maintains its charging state across multiple sampling cycles, eliminating dead time and maintaining both statistical accuracy and response time performance.
2Productivity
If the response time is reduced, then the working efficiency is improved, but the jitter tolerance deteriorates
Solution Approach 1:
The patent dynamically adjusts the charging parameters of the capacitance components based on operating conditions. By changing charging voltage levels, current magnitudes, or timing parameters, the circuit can achieve fast response (high working efficiency) while maintaining sufficient jitter tolerance through optimized parameter selection that balances speed and stability.
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor the charging state of capacitance components and adjust subsequent charging actions accordingly. This feedback control ensures that the circuit maintains optimal performance by preventing over-charging or under-charging, thereby preserving jitter tolerance while achieving reduced response time for improved working efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the working efficiency of the clock and data recovery circuit by reducing response time and improving jitter tolerance, allowing for more effective signal synchronization.
Implementation Method 1
The first voting circuit is coupled to the phase detection circuit and configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result
Data Source
AI summary
A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.