Clock Recovery Calibration for MIPI C-PHY Signal Receivers
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Solution Overview
Problem
Current signal receiving devices face challenges in efficiently recovering clock and data signals from MIPI C-PHY interfaces, particularly due to varying signal levels and the need to mitigate jitter characteristics, which complicates the recovery process and requires additional circuitry.
Innovation Solution
A signal receiving device comprising a transition detecting device, clock data recovering device, calibration device, decoder, and de-mapper that generates differential signals, comparison signals, and gain control signals to recover clock and data signals, eliminating the need for separate jitter adjustment circuits by setting reference signal levels to minimize transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate jitter adjustment circuits are added to recover clock and data signals, then signal recovery accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines the jitter adjustment function into the existing clock data recovery device, eliminating the need for separate jitter adjustment circuits. The processing circuitry integrates both clock recovery and jitter mitigation in a single unified structure, thereby maintaining signal recovery accuracy while reducing device complexity.
Solution Approach 2:
The clock data recovery device is designed to perform multiple functions: clock signal recovery, data signal recovery, and jitter characteristic mitigation. This multi-functional approach allows a single device to handle tasks that previously required separate dedicated circuits, reducing overall system complexity.
2Reliability
If additional circuitry is added to mitigate jitter characteristics, then signal recovery reliability is improved, but device size increases
Solution Approach 1:
The jitter mitigation functionality is merged into the existing clock data recovery circuitry rather than being implemented as separate additional circuits. This integration approach maintains signal recovery reliability through jitter compensation while avoiding the need for extra physical space that separate circuits would require.
3Measurement precision
If complex processing is used to recover clock and data signals, then recovery precision is improved, but processing time increases
Solution Approach 1:
The processing circuitry is pre-configured with the capability to perform complex signal processing operations for clock and data recovery. By having the processing logic already in place and optimized, the system can execute precise recovery operations without incurring excessive processing delays during actual signal reception.
Data Source
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AI summary
A signal receiving device including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.