Clock Recovery Circuit With Configurable Delay for C-PHY Jitter
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Solution Overview
Problem
The high data rates of C-PHY communication interfaces are limited by circuit switching jitter, leading to signal eye closure and difficulties in clock recovery, which hampers the efficient transmission of high bits-per-symbol data.
Innovation Solution
A clock recovery circuit comprising switch circuitry and latch circuitry generates a cyclical signal based on differential data signals, with configurable delays to mitigate jitter effects, enabling improved clock recovery and high-frequency data sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If C-PHY interface uses high data rates with embedded clock, then communication efficiency increases, but circuit switching jitter causes signal eye closure and clock recovery difficulties
Solution Approach 1:
The patent introduces an intermediary clock recovery circuit between the received differential data signals and the sampling circuitry. This intermediary circuit generates a clean cyclical clock signal by detecting transitions in the jittered data signals and applying configurable delays, thereby mediating the harmful jitter effects and enabling reliable high-speed data recovery
Solution Approach 2:
The patent applies preliminary action by pre-processing the received data signals through transition detection and delay configuration before the actual sampling operation. The clock recovery circuit proactively generates the cyclical signal in advance of each data sampling event, ensuring that sampling occurs at optimal timing points despite jitter in the original signals
2Reliability
If conventional clock recovery methods are used, then circuit complexity remains low, but clock recovery fails at high data rates due to jitter
Solution Approach 1:
The patent segments the clock recovery function into distinct modular components: transition detection circuitry that identifies signal edges, configurable delay elements that adjust timing, and cyclical signal generation logic that produces the final clock waveform. This segmentation allows each component to be optimized independently while maintaining overall reliability without excessive complexity
Solution Approach 2:
The clock recovery circuit is designed with universal applicability to C-PHY interfaces operating at various data rates. The configurable delay mechanism allows the same circuit architecture to adapt to different timing requirements, making it a multi-functional solution that maintains reliability across different operating conditions without requiring separate specialized circuits for each rate
Data Source
AI summary
Techniques and mechanisms for a clock recovery circuit to generate a cyclical signal based on data signals which are susceptible to circuit switching jitter. In an embodiment, a clock recovery circuit comprises switch circuitry which receives a first signal representing a logical combination of multiple pulsed signals (which, in turn, are each based on a different respective differential data signal). The switch circuitry provides to latch circuitry of the clock recovery circuit a second signal based on the first signal. The latch circuitry generates a cyclical signal based on the second signal, and transitions the switch circuitry between an open-circuit state and a closed-circuit state. In another embodiment, the latch circuitry implements a predetermined and configurable time period between a transition of the cyclical signal and a next subsequent logic state transition of the cyclical signal.