Clock Recovery Over Data Links for Low-Phase-Noise Synchronization
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Solution Overview
Problem
Existing systems face challenges in synchronizing distributed components across integrated circuits or remote locations due to the complexity and precision required for clock synchronization, often necessitating dedicated wires or traces, which can be cumbersome and difficult to manage, especially in systems with high precision needs.
Innovation Solution
Utilizing high-speed data interfaces to transmit timing information between components, allowing them to generate synchronized clocks without dedicated synchronization wires, and employing methods like oversampling or clock edge detection and reconstruction to achieve phase and period synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated wires or traces are used for clock synchronization, then phase synchronization precision is improved, but system complexity and board space requirements increase
Solution Approach 1:
The patent transmits clock timing information as digital data through existing data interfaces rather than using dedicated clock traces. The receiving component reconstructs the clock signal from this transmitted timing data, effectively creating a copy of the clock signal through information processing rather than physical signal propagation.
Solution Approach 2:
The patent replaces the physical electrical signal transmission method (dedicated clock traces) with a digital information processing method. Instead of transmitting analog clock signals through PCB traces, the system transmits timing information as digital data and reconstructs the clock signal through logical operations and counters.
2Reliability
If dedicated wires or traces are used for clock synchronization, then clock signal distribution is improved, but PCB board space and routing complexity increase
Solution Approach 1:
The patent makes existing data interfaces serve dual purposes: they continue to transmit data while also transmitting clock timing information. This eliminates the need for separate dedicated clock distribution traces, allowing the same physical infrastructure to perform multiple functions.
Solution Approach 2:
The clock signal is reconstructed at the receiving end from transmitted timing information, creating a local copy of the clock signal without requiring physical connection through dedicated traces. This copying approach eliminates the need for extensive clock signal routing across the PCB.
3Measurement precision
If phase differences are compensated between generated clock and received synchronization signals, then synchronization accuracy is improved, but system complexity increases
Solution Approach 1:
The patent employs feedback mechanisms where the transmitting component monitors its own clock timing and incorporates this information into the transmitted timing data. The receiving component uses this feedback information to accurately reconstruct the clock signal, compensating for any phase differences without requiring complex external calibration.
Solution Approach 2:
The patent performs preliminary measurement and compensation of timing characteristics at the transmitting end before signal transmission. By pre-calculating and embedding timing correction data in the transmitted information stream, the system eliminates the need for complex real-time phase adjustment circuits at the receiving end.
Data Source
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AI summary
A system includes a first integrated circuit device, a second integrated circuit device, and a reference clock provided to the first and second integrated circuit devices. The first integrated circuit device detects a first edge of a first clock utilized by the first integrated circuit device, detects a second edge of the first clock, determines a first count of cycles of the reference clock between the first edge and the second edge, and communicates the first count to the second integrated circuit device. The second integrated circuit device receives the first count, provides a third edge of a second clock utilized by the second integrated circuit device, determines that a first number of cycles of the reference clock since providing the third edge is equal to the first count, and provides a fourth edge of the second clock in response to determining that the first number of cycles is equal to the first count.