Clock Recovery Over Data Links for Low-Phase-Noise Synchronization
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Solution Overview
Problem
Existing systems face challenges in synchronizing clocks across distributed components without dedicated synchronization wires or traces, particularly in high-precision applications where phase noise and phase differences are critical, and the complexity of routing synchronization signals adds to system complexity.
Innovation Solution
The system employs a common reference clock and high-speed data interfaces to transmit timing information, allowing integrated circuit devices to synchronize their clocks by detecting clock edges, counting cycles, and communicating these counts to recreate the clock signal, thereby eliminating the need for dedicated synchronization wires and correcting phase delays through additional timing information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated wires or traces are used for clock synchronization, then clock synchronization reliability is improved, but device complexity and board space increase
Solution Approach 1:
The patent combines clock synchronization functionality with existing data communication channels. The timing information is embedded within data packets transmitted over existing interfaces (e.g., PCIe, USB, Ethernet), eliminating the need for separate dedicated synchronization wires or traces. This merging approach maintains synchronization reliability while reducing system complexity and board space requirements.
Solution Approach 2:
The existing data communication interface is made multi-functional by enabling it to carry both data traffic and clock synchronization information simultaneously. The system uses the same physical infrastructure for both purposes, making the synchronization mechanism universal and applicable to various communication protocols without requiring additional dedicated infrastructure.
2Measurement precision
If dedicated wires or traces are used for clock synchronization, then phase synchronization precision is improved, but routing complexity increases
Solution Approach 1:
The patent introduces timing information packets as an intermediary carrier that conveys clock synchronization data over existing communication channels. These packets contain timestamp and timing correction information that mediates the synchronization process, enabling precise phase alignment without requiring complex physical routing of dedicated synchronization traces through the system.
3Device complexity
If clock synchronization is implemented without dedicated wires, then device complexity is reduced, but phase noise increases
Solution Approach 1:
The system implements feedback mechanisms where timing information is continuously monitored and corrected. The receiving device extracts timing data from incoming packets, compares it with its local clock, and applies phase corrections to maintain synchronization. This feedback loop compensates for the increased phase noise inherent in using shared data channels instead of dedicated synchronization wires.
Solution Approach 2:
The system performs preliminary timing measurements and corrections by embedding timing information in advance within data packets. The transmitting device prepares and sends timing correction data before the receiving device needs to synchronize its clock, allowing the receiver to proactively adjust its phase rather than reacting to synchronization errors after they occur.
Data Source
AI summary
A system includes a first integrated circuit device, a second integrated circuit device, and a reference clock provided to the first and second integrated circuit devices. The first integrated circuit device detects a first edge of a first clock utilized by the first integrated circuit device, detects a second edge of the first clock, determines a first count of cycles of the reference clock between the first edge and the second edge, and communicates the first count to the second integrated circuit device. The second integrated circuit device receives the first count, provides a third edge of a second clock utilized by the second integrated circuit device, determines that a first number of cycles of the reference clock since providing the third edge is equal to the first count, and provides a fourth edge of the second clock in response to determining that the first number of cycles is equal to the first count.