Clock Recovery Delay Control for Stable Setup and Hold Margin
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Solution Overview
Problem
Existing clock recovery devices in display devices suffer from errors in delay time due to variations in input/output capacitances, leading to reduced setup or hold margin and limited application range.
Innovation Solution
A clock recovery device with a delay controller that adjusts delay time by using inverters of varying sizes based on input frequency, generating multi-level clock signals and correcting delay times to a reference, thereby stabilizing the delay time across different capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a voltage-controlled delay line is used to generate clock signals, then clock signals can be generated with delay, but delay time errors occur due to differences in capacitor capacity or line length between the master clock signal path and the delay line path
Solution Approach 1:
The patent implements a feedback mechanism where the delay controller receives delayed clock signals from the delay line, compares the actual delay time with the reference delay time, and generates a selection signal to adjust the inverter chain configuration. This closed-loop feedback system continuously corrects delay time errors caused by manufacturing variations in capacitors and line lengths, ensuring accurate delay timing despite process variations.
Solution Approach 2:
The patent changes the delay time parameter by dynamically adjusting the number of inverters in the delay chain based on the selection signal. Instead of relying on fixed capacitor values that suffer from manufacturing variations, the system varies the delay parameter by selecting different numbers of inverters (e.g., 2 to 6 inverters) to compensate for delay errors and achieve the target reference delay time.
2Device complexity
If the delay time is fixed based on constant capacitor values, then the circuit design is simplified, but the setup or hold margin is damaged due to delay time errors, reducing the range of application
Solution Approach 1:
The patent transforms the static delay time into a dynamic parameter that can be adjusted based on operating conditions. The delay controller dynamically selects the number of inverters in the delay chain according to the input frequency and detected delay time, allowing the system to adapt to different application requirements and maintain optimal setup or hold margins across various operating conditions.
Solution Approach 2:
The patent segments the delay line into multiple adjustable inverter stages (2 to 6 inverters) that can be selectively activated. This segmentation allows fine-grained control over the total delay time, enabling the system to compensate for manufacturing variations and optimize performance for different application scenarios without requiring a completely different circuit design.
3Manufacturing precision
If inverters of varying sizes are used to adjust delay time, then the delay time can be corrected to reference delay time, but the device complexity increases
Solution Approach 1:
The patent applies local quality by using inverters of different sizes (large size for low frequency, small size for high frequency) at different positions or under different conditions within the delay chain. This localized optimization allows the delay controller to achieve accurate delay time correction across different frequency ranges while managing overall device complexity through targeted rather than uniform design.
Data Source
AI summary
A clock recovery device may include a clock generator configured to generate a master clock signal from embedded transmission data, a delay line for generating multi-level clock signals by delaying the master clock signal by a preset reference delay time unit based on an input frequency, a delay controller configured to receive two clock signals delayed by a reference delay time unit among the multi-level clock signals and detect delay time, output a selection signal based on the delay time and the reference delay time, correct the delay time of the master clock signal to the reference delay time based on the selection signal, and output the master clock signal corrected to the reference delay time to the delay line, and a data recovery module configured to recover the multi-level clock signal corrected to the reference delay time through the delay line.