Clock and Data Recovery Circuit Using Delayed SERDES Sampling
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Solution Overview
Problem
Programmable logic devices (PLDs) without dedicated multi-gigabit transceiver (MGT) circuits face challenges in exchanging serial data at high rates, as they lack the necessary transceiver capability to facilitate multi-gigabit data transfer.
Innovation Solution
A clock and data recovery circuit comprising multiple receiver segments with programmable delays and error correction blocks that deserializes and merges data streams to recover data signals, enabling data recovery without dedicated transceiver circuitry by using input/output pins and interconnect elements within the PLD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated multi-gigabit transceiver (MGT) circuits are used, then multi-gigabit data transfer capability is achieved, but device complexity and cost increase
Solution Approach 1:
The patent divides the data transfer function into multiple segments by using multiple standard transceiver pins (e.g., 4 pins for 10Gbps transfer) that each operate at lower individual rates. These segmented channels are then combined through parallel processing and error correction logic to achieve the aggregate multi-gigabit transfer rate, eliminating the need for a single dedicated MGT circuit.
Solution Approach 2:
The patent makes standard transceiver pins and programmable logic elements perform multiple functions: data reception, parallel-to-serial conversion, error detection, error correction, and clock recovery. This multi-functionality allows standard components to replace specialized MGT circuitry, reducing device complexity while maintaining high-speed capability.
2Device complexity
If standard transceiver pins are used without dedicated MGTs, then device complexity is reduced, but data transfer rate and reliability deteriorate
Solution Approach 1:
The patent implements feedback mechanisms through error detection and correction blocks that monitor data integrity across multiple parallel channels. Error correction codes (ECC) provide feedback about data quality, allowing the system to detect and correct errors that occur during high-speed parallel-to-serial conversion, thereby maintaining reliability without dedicated MGTs.
Solution Approach 2:
The patent performs preliminary error detection and correction actions on data before final serialization and output. By proactively identifying and correcting errors in the parallel data streams before they are combined into the final serial output, the system prevents error propagation and maintains high data transfer reliability.
3Adaptability or versatility
If multiple receiver segments with programmable delays are used, then data recovery capability is improved, but circuit complexity increases
Solution Approach 1:
The patent employs dynamic programmable delay elements in each receiver segment that can be adjusted based on timing requirements and data rate. This dynamic adjustability allows the same receiver segment architecture to adapt to different data rates and timing conditions, improving data recovery capability while avoiding the need for multiple fixed-architecture receiver segments.
Data Source
AI summary
A method and apparatus for a clock and data recovery circuit that includes a set of serializer/deserializer (SERDES) circuits that are adapted to sample progressively delayed versions of an input data stream. The sampling rate is slightly higher than the data rate of the input data stream, which produces duplicate bits in the detected data stream. Error and offset matrices are used to generate an index pointer into a detected data matrix to extract the correct data bits from the duplicate bits of the detected data matrix. Down-sampling of the corrected data is performed to populate a ring buffer. Data is then extracted from the ring buffer using a clock signal whose frequency is adapted from the sampling clock signal used by the SERDES to prevent underflow/overflow of the ring buffer.