Clock Recovery Circuit for Display Data Synchronization
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Solution Overview
Problem
Display devices face challenges in accurately recovering clock and data signals due to asynchronous inputs, leading to instability in data recovery across multiple data drive ICs, which complicates the control of N-bit data strings and results in signal delays.
Innovation Solution
A data drive circuit with a clock and data recovery part that uses an internal clock to recover a test data pattern, compares it with a reference pattern to generate a control signal for synchronizing the clock with the input data, and selects the appropriate clock phase from divided clocks to ensure accurate clock recovery and data synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If N different asynchronous signals are generated at different receivers to handle N-bit data strings, then the data transmission capacity is improved, but the system control complexity increases and signal synchronization becomes difficult
Solution Approach 1:
The N-bit data string is segmented into N separate data signals, with each receiver handling one bit. Each receiver generates one phase of clock signal, resulting in N phases total. This segmentation allows parallel processing of multiple bits while maintaining manageable control complexity at each individual receiver node.
Solution Approach 2:
The patent combines multiple asynchronous clock signals from different receivers into a unified synchronized clock system. By using a reference clock signal distributed to all receivers and combining their individual clock generations, the system achieves synchronized operation across all N receivers, reducing overall control complexity while maintaining high data transmission capacity.
2Adaptability or versatility
If the input data is asynchronous with the clock, then the receiver can handle variable data rates, but accurate recovery of received information becomes difficult
Solution Approach 1:
The patent implements feedback mechanisms where each receiver monitors its recovered data and clock synchronization status. The system uses feedback loops to adjust clock phase and timing based on detected data patterns, ensuring accurate recovery even when input data arrives asynchronously. This feedback enables dynamic adaptation to varying data rates while maintaining precision.
Solution Approach 2:
The system dynamically changes clock parameters (phase, frequency, timing) based on the actual arrival timing of asynchronous data signals. Each receiver adjusts its local clock parameters to match the incoming data rate, enabling accurate sampling and recovery of information regardless of variable data rates from the transmitter.
3Ease of manufacture
If N different delays are generated at different receivers, then each receiver can be optimized for its specific data path, but controlling N different asynchronous signals becomes difficult
Solution Approach 1:
The patent designs each receiver with universal functionality to handle multiple aspects of signal processing (clock generation, data recovery, synchronization) using the same architectural blueprint. This universal design allows each receiver to be optimized independently while maintaining ease of operation across the entire system, as all receivers operate according to the same standardized protocol and timing reference.
Data Source
AI summary
The present disclosure relates to a data drive circuit capable of increasing clock and data recovery stability by generating a clock synchronized with input data, a clock recovery method thereof, and a display drive device having the same, and the data drive circuit according to an aspect includes a receiver including a clock and data recovery part configured to recover a test data pattern from input data using an internal clock, and a data comparator configured to compare the recovered test data pattern with a predetermined reference data pattern to generate a control signal according to a degree of asynchronicity between the recovered test data pattern and the reference data pattern, wherein the clock and data recovery part recovers a clock synchronized with the input data according to the control signal, and recovers control information and image data from the input data using the recovered clock.