Clock Recovery Circuit with Dynamic Phase Offset Estimation
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Solution Overview
Problem
Conventional clock recovery apparatuses in Ethernet networks face challenges in synchronizing sampling clocks between the receiving and transmitting ends, especially in long-term transmission or environments with large phase offsets, due to the inflexibility of fixed-length statistical windows and unpredictable phase offsets.
Innovation Solution
A clock recovery apparatus comprising an analog-to-digital converter, a multi-phase clock generating circuit, and a clock recovery circuit with a phase detector, loop filter, phase-offset estimator, and phase adjusting circuit, which detects phase shifts, estimates phase-offset parameters, and automatically adjusts the sampling clock phase to synchronize clocks, using a numerically controlled oscillator for predictive adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed-length statistical window is used in conventional clock recovery apparatus, then the circuit structure is simple, but the synchronization accuracy deteriorates in long-term transmission or environments with large phase offsets
Solution Approach 1:
The patent implements a dynamic statistical window length adjustment mechanism where the window length is no longer fixed but adapts based on the detected phase offset magnitude. When large phase offsets are detected, the window length is extended to accumulate sufficient statistical data for accurate synchronization, whereas for small phase offsets, a shorter window is used to maintain responsiveness. This dynamic adjustment resolves the contradiction by making the system structure adaptive rather than static.
Solution Approach 2:
The patent changes the parameter of statistical window length from a fixed value to a variable that can be adjusted based on operating conditions. The system monitors phase offset characteristics and dynamically modifies the window length parameter to optimize synchronization accuracy for different transmission scenarios, thereby improving measurement precision without requiring fundamentally more complex circuitry.
2Measurement precision
If the statistical window length is extended to improve synchronization accuracy, then the measurement precision improves, but the response time to phase offset changes increases
Solution Approach 1:
The system dynamically adjusts the statistical window length based on the magnitude of detected phase offsets. For large phase offsets, a longer window is used to ensure accurate measurement, while for small phase offsets or during transient conditions, a shorter window provides faster response. This dynamic behavior resolves the contradiction by optimizing the window length for each specific operating condition rather than using a consistently long window.
Solution Approach 2:
The patent implements a preliminary detection phase where the system quickly identifies the magnitude of phase offsets before committing to a longer statistical window for accurate synchronization. This preliminary action allows the system to prepare the appropriate window length in advance, reducing the overall response time while maintaining accuracy when needed.
3Device complexity
If conventional clock recovery apparatus is used, then the device complexity is low, but the packet error rate increases in environments with significant phase discrepancies
Solution Approach 1:
The patent modifies the operational parameters of the clock recovery apparatus by dynamically adjusting the statistical window length based on detected phase offset characteristics. This parameter change enables the system to maintain low device complexity while significantly improving reliability in environments with significant phase discrepancies, as the adaptive window length ensures accurate synchronization even under challenging conditions.
Data Source
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AI summary
A clock recovery apparatus and a clock recovery method are provided. The clock recovery apparatus includes an analog-to-digital converter (ADC), a multi-phase clock generating circuit, and a clock recovery circuit. The ADC samples an analog input signal by using a sampling clock to output a digital input signal. The multi-phase clock generating circuit outputs the sampling clock and determines a phase of the sampling clock according to a phase selection signal. During a first period, the clock recovery circuit generates the phase selection signal according to phase shift of the digital input signal, and estimates a phase-offset parameter according to the digital input signal. During a second period, the clock recovery circuit generates the phase selection signal according to the phase-offset parameter generated in the first period and the phase shift of the digital input signal.