Clock Recovery Frequency Detector Using Edge-Based Single-Bit Logic
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Solution Overview
Problem
Existing frequency acquisition methods for clock and data recovery circuits, such as phase-frequency detectors and counter-based detectors, are inefficient, particularly with low-swing signals and require complex multi-bit arithmetic operations, making them difficult to implement effectively.
Innovation Solution
A frequency detector circuit utilizing a transition detector, delay circuits, and combinational logic to generate UP and DOWN signals based on edge outputs, allowing for efficient frequency detection without multi-bit arithmetic operations, and enabling conversion to phase detection mode via a selection signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase-frequency detectors or counter-based frequency detectors are used for frequency acquisition, then frequency detection capability is provided, but device complexity increases due to multi-bit counters and arithmetic operations
Solution Approach 1:
The frequency detection function is segmented into multiple single-bit detectors operating at different clock phases. Each detector processes only one bit of frequency information at a specific phase, avoiding the need for complex multi-bit counters. The results from multiple phase-segmented detectors are combined to achieve complete frequency detection capability.
Solution Approach 2:
The patent replaces the mechanical counting and multi-bit arithmetic operations with electrical signal processing using single-bit logic gates and phase-shifted clock signals. This substitution eliminates the need for complex digital arithmetic circuits while maintaining frequency detection accuracy through parallel single-bit processing.
2Measurement precision
If traditional frequency acquisition circuits are used, then frequency detection is possible, but ease of operation deteriorates due to difficulty in implementing multi-bit arithmetic operations
Solution Approach 1:
The frequency acquisition task is divided into multiple simple single-bit detection operations performed in parallel at different phases. Each phase processes independent single-bit signals through simple logic gates, making the implementation straightforward and avoiding complex multi-bit arithmetic operations.
Solution Approach 2:
Multiple simple single-bit detection results from different phases are merged through logical combination to achieve the complete frequency acquisition function. This merging approach allows complex frequency detection to be built from simple, easily implementable single-bit detectors.
3Measurement precision
If multi-bit counters and arithmetic operations are used for frequency detection, then comprehensive frequency measurement is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The frequency measurement function is segmented into multiple independent single-bit detection stages operating at different phases. Each stage uses simple logic gates with relaxed manufacturing tolerances, and the combined results achieve high overall measurement precision without requiring high-precision multi-bit arithmetic circuits.
Solution Approach 2:
The patent uses simple, low-cost single-bit logic gates instead of expensive multi-bit arithmetic circuits. Each single-bit detector is a simple, easily manufactured component that can be implemented with standard logic gates, reducing manufacturing precision requirements while maintaining functional accuracy.
Data Source
AI summary
A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.