Clock Data Recovery with Pattern-Filtered Edge Equalization

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Solution Overview

Problem

Bang-Bang clock data recovery (CDR) apparatuses face challenges in eliminating or reducing the impact of inter-symbol interference (ISI) on edge information, which affects locking capability and increases clock recovery jitter.

Innovation Solution

The proposed solution includes a clock data recovery apparatus comprising an equalizer, a phase detector, and an oscillation circuit, where the equalizer generates equalized data, the phase detector performs pattern-filtering to reduce ISI, and the oscillation circuit generates a clock signal based on the filtered data, with adaptive adjustment of equilibrium coefficients to improve resistance against ISI.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Bang-Bang CDR apparatus performs locking by using edge information, then locking capability is achieved, but inter-symbol interference impacts on edge are not eliminated or decreased

Engineering Contradiction:
Improvelocking capabilityVSAvoidinter-symbol interference impact
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the equalization process into two distinct parts: a first equalizer processes data using a first equilibrium coefficient, and a second equalizer processes edge data using a second equilibrium coefficient. This segmentation allows independent optimization of each equalizer's parameters, enabling the second equalizer to specifically target and reduce inter-symbol interference on edges while the first equalizer handles overall data equalization, thus resolving the contradiction between maintaining locking capability and eliminating ISI impacts.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by using different equilibrium coefficients for different parts of the signal processing chain. The first equilibrium coefficient is used for general data equalization, while the second equilibrium coefficient is specifically optimized for edge data processing. This localized optimization allows the system to tailor the equalization characteristics to the specific requirements of edge information, reducing inter-symbol interference precisely where it matters most for locking capability.

Inventive Principle:
Principle #3Local quality

2Reliability

If inter-symbol interference impacts locking capability, then CDR locking is affected, but jitter of recovery clock increases

Engineering Contradiction:
Improvelocking capabilityVSAvoidclock recovery jitter
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

By segmenting the equalization into two parallel paths with different equilibrium coefficients, the system can independently optimize for both locking capability and jitter reduction. The first equalizer maintains overall signal integrity for reliable locking, while the second equalizer specifically processes edge information to minimize jitter, thereby resolving the contradiction between locking reliability and clock recovery precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter (equilibrium coefficient) based on the specific processing stage: the first equilibrium coefficient for general data equalization and the second equilibrium coefficient for edge data equalization. This parameter differentiation allows the system to optimize performance metrics differently for each stage, reducing both locking issues and jitter simultaneously.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10855437B1Clock data recovery apparatus and operation method thereof
Publication Date: 2020.12.01 FARADAY TECH CORP
  • US10855437B1 patent drawing
  • US10855437B1 patent drawing
  • US10855437B1 patent drawing

AI summary

The present invention provides a clock data recovery apparatus and an operation method thereof. The clock data recovery apparatus includes an equalizer, a phase detector, a charge pump, and an oscillation circuit. The equalizer is configured to equalize raw data to generate equalized data. The phase detector is coupled to the equalizer to receive the equalized data. The phase detector is configured to generate a detection result according to the equalized data. The phase detector performs pattern-filtering on the equalized data to filter out at least one pattern. The charge pump is coupled to the phase detector to receive the detection result. The charge pump is configured to generate a control signal according to the detection result. The oscillation circuit is coupled to the charge pump to receive the control signal. The oscillation circuit is configured to generate a clock signal according to the control signal.