Clock Recovery Frequency Detector Using Edge Voting Logic

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Solution Overview

Problem

Existing frequency acquisition methods in clock and data recovery circuits, such as phase-frequency detectors and counter-based detectors, are inefficient and complex, particularly when dealing with low-swing signals and require multi-bit arithmetic operations, making them difficult to implement effectively.

Innovation Solution

A frequency detector circuit utilizing a transition detector, delay circuits, and combinational logic to generate UP and DOWN signals based on edge outputs, allowing for efficient frequency detection without multi-bit arithmetic operations, and enabling conversion to phase detection mode via a selection signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If phase-frequency detectors or counter-based frequency detectors are used for frequency acquisition, then frequency detection capability is provided, but device complexity increases due to multi-bit counters and arithmetic operations

Engineering Contradiction:
Improvefrequency detection accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The frequency detector is divided into separate functional modules: a transition detector for edge detection, delay circuits for timing control, and combinational logic for UP/DOWN signal generation. This segmentation allows each module to perform a specific function with simple logic, avoiding the need for complex multi-bit counters and arithmetic operations while maintaining accurate frequency detection capability.

Inventive Principle:
Principle #1Segmentation

2Productivity

If rotation frequency detectors are used, then frequency acquisition is enabled, but reliability decreases when dealing with low-swing signals

Engineering Contradiction:
Improvefrequency acquisition capabilityVSAvoidsignal detection reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A transition detector is introduced as an intermediary component between the low-swing signal source and the frequency detection logic. This transition detector reliably detects signal edges and generates clean transition signals that can be processed by the delay circuits and combinational logic, ensuring accurate frequency acquisition even when the input signals have low swing.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If multi-bit counters and arithmetic operations are used in frequency detectors, then frequency measurement capability is achieved, but ease of manufacture decreases due to implementation difficulty

Engineering Contradiction:
Improvefrequency measurement accuracyVSAvoidimplementation ease
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent replaces complex mechanical/computational systems (multi-bit counters and arithmetic operations) with a simpler electronic logic system. By using transition detection combined with delay circuits and basic combinational logic gates, the system achieves frequency measurement functionality through straightforward digital logic operations that are easier to manufacture and implement in standard CMOS technology.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11711199B2Efficient frequency detectors for clock and data recovery circuits
Publication Date: 2023.07.25 SAMSUNG DISPLAY CO LTD
  • US11711199B2 patent drawing
  • US11711199B2 patent drawing
  • US11711199B2 patent drawing

AI summary

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.