Clock Data Recovery Circuit for Fast PLL False Lock Detection
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Solution Overview
Problem
Existing clock data recovery methods, such as those using Phase Locked Loops (PLL), often experience false lock conditions where the frequency of the reproduced clock signal is locked at an incorrect frequency, leading to inaccurate data reception, and current detection methods require significant data input and time to accurately determine false lock occurrences.
Innovation Solution
A clock data recovery circuit that includes a receiver circuit, a PLL circuit, and a false lock detection circuit, which detects false lock patterns directly from sampled data rather than calculating occurrence probabilities, allowing for quicker detection of false lock conditions by identifying specific patterns like '0, 1, 0, 1, ...' within the sampled data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If occurrence probability calculation method is used to detect false lock, then detection accuracy is improved, but detection time increases significantly
Solution Approach 1:
The invention extracts and monitors only the specific predetermined pattern (e.g., '010101...' or '101010...') from the sampled data, rather than calculating occurrence probabilities of all possible patterns. This selective extraction of the critical false lock pattern enables rapid detection without the computational overhead of comprehensive probability calculations, directly resolving the contradiction between detection accuracy and detection time.
2Reliability
If great deal of data is input to increase occurrence probability calculation accuracy, then false lock detection reliability is improved, but detection speed decreases
Solution Approach 1:
The invention performs preliminary action by pre-defining the specific patterns that indicate false lock conditions (such as alternating '010101...' or '101010...'). By having these patterns predetermined and ready for direct matching, the system can immediately detect false lock when these patterns appear in the sampled data, eliminating the need to accumulate large amounts of data for statistical analysis and thus maintaining both high reliability and fast detection speed.
3Measurement precision
If occurrence probability method is used, then comprehensive analysis is achieved, but system complexity increases
Solution Approach 1:
The invention uses a simplified copying approach by directly comparing the sampled data against a predetermined pattern template (e.g., '010101...' or '101010...'). Instead of implementing complex probability calculation circuits that would require numerous logic gates and computational resources, the system simply checks whether the sampled sequence matches the expected false lock pattern, dramatically reducing circuit complexity while maintaining detection precision.
Data Source
AI summary
A clock data recovery circuit has: a receiver circuit configured to receive a serial data including a predetermined pattern and to sample the serial data in synchronization with a clock signal to generate a sampled data; a PLL circuit configured to perform clock data recovery based on the sampled data to generate the clock signal; and a false lock detection circuit configured to detect false lock of the PLL circuit by detecting a false lock pattern included in the sampled data. The false lock pattern is a pattern obtained by the receiver circuit sampling the predetermined pattern when the false lock of the PLL circuit occurs.