Clock Data Recovery Circuit With False-Lock Avoidance Precharge
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Solution Overview
Problem
Existing high-speed serial data communication systems using embedded clock schemes often experience false locks in clock data recovery circuits, leading to unreliable data reception due to external noise and PLL malfunction, where the frequency of the reproduced clock signal gets locked to an incorrect frequency.
Innovation Solution
A synchronizing circuit that includes a charge pump for generating phase control voltage, a phase control circuit for phase control of the reproduced clock signal, and a false-lock avoidance circuit that precharges a line when the phase control voltage falls below a lower-limit reference voltage and stops precharging when it exceeds an upper-limit reference voltage, ensuring the phase control voltage remains high even during external noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL circuit is used for clock data recovery, then the reproduced clock signal can be synchronized with the reference clock signal, but false lock may occur when external noise causes the phase control voltage to be fixed at a low level
Solution Approach 1:
The false-lock avoidance circuit proactively monitors the phase control voltage and activates the precharge transistor to precharge the first line when the voltage drops to a low level, preventing false lock before it occurs rather than reacting after false lock has occurred
Solution Approach 2:
The false-lock avoidance circuit continuously monitors the phase control voltage level and provides feedback control by activating the precharge transistor when the voltage drops below a threshold, creating a closed-loop system that maintains voltage within acceptable ranges
2Adaptability or versatility
If the phase control voltage is allowed to drop to low levels during noise interference, then the charge pump can respond to phase differences, but false lock occurs and synchronization reliability deteriorates
Solution Approach 1:
The system dynamically changes the voltage level parameter of the phase control signal by introducing a precharge mechanism that maintains the first line at a high voltage level, preventing the phase control voltage from dropping to levels that cause false lock while preserving phase control functionality
3Ease of operation
If the PLL circuit starts initial synchronization with phase control voltage at zero level, then the circuit can initialize, but false lock may occur at incorrect frequency
Solution Approach 1:
The false-lock avoidance circuit performs preliminary action by precharging the first line before initial synchronization occurs, ensuring the phase control voltage starts at a high level rather than zero, which prevents false lock during the initialization process while maintaining ease of operation
Data Source
AI summary
A synchronizing circuit that is capable of generating a reproduced clock signal synchronized with a reference clock signal without causing a false lock and a clock data recovery circuit including the same are provided. To generate a clock signal synchronized with a reference clock signal associated with a data transition point that appears every predetermined period in an input data signal, the following false-lock avoidance processing is performed. That is, precharging of a first line is started when a phase control voltage applied to the first line by a charge pump falls below a lower-limit reference voltage, and the precharging of the first line is continued until the phase control voltage exceeds an upper-limit reference voltage.