Dual-Detector Clock Recovery Circuit for Fast Low-Power Wake-Up
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Solution Overview
Problem
Conventional data and clock recovery (CDR) circuits in high-speed USB and PCIe fields face high latency and high power consumption when switching from power-saving modes to normal operation, particularly due to the continuous operation of high-speed phase detectors in power-saving modes, which limits their ability to enter power-off modes efficiently.
Innovation Solution
The proposed CDR circuit incorporates a first and second selecting circuit, a high-speed and low-speed phase detector, a charge pump, a voltage control oscillator, and a frequency divider, utilizing multiplexers and phase detectors to selectively engage high-speed or low-speed components based on mode selection signals, allowing for efficient switching between power-saving and normal modes with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the high-speed phase detector is continuously operated in power-saving mode to achieve low latency wake-up, then the wake-up time is reduced, but the power consumption increases significantly (consuming 70% of total circuit energy)
Solution Approach 1:
The phase detector function is segmented into two independent detectors: a low-speed phase detector for power-saving mode operation and a high-speed phase detector for normal mode operation. This segmentation allows each detector to be optimized for its specific operating condition, with the low-speed detector consuming minimal power during power-saving mode while the high-speed detector remains dormant until needed for rapid wake-up transitions.
Solution Approach 2:
The system dynamically switches between different phase detectors based on the operational mode. A mode selection signal controls which phase detector is active, enabling the circuit to adapt its power consumption and performance characteristics to match the current operational requirements. This dynamic switching resolves the contradiction by allowing low power consumption during power-saving mode while maintaining the capability for low-latency wake-up when transitioning to normal mode.
2Use of energy by moving object
If the conventional CDR circuit enters power-off mode to reduce power consumption, then energy savings are achieved, but the locking time exceeds 20 μs which is unacceptable for low-latency requirements
Solution Approach 1:
The low-speed phase detector maintains a reduced operational state during power-saving mode, performing preliminary clock recovery and phase detection functions at lower power consumption. This preliminary action keeps the voltage control oscillator and frequency divider in a ready state, so when transitioning to normal mode, the high-speed phase detector can quickly take over without requiring a complete re-locking sequence, thus achieving both power savings and fast wake-up times.
3Loss of time
If the CDR circuit is fully turned on in power-saving mode to meet low latency requirements, then wake-up performance is maintained, but the power consumption becomes very high and prevents entry into power-off mode
Solution Approach 1:
Different parts of the CDR circuit are placed in different operational states during power-saving mode. The low-speed phase detector operates at minimal power consumption, while the high-speed phase detector remains off. The voltage control oscillator and frequency divider operate at reduced power levels. This local quality differentiation allows the circuit to achieve both low power consumption and acceptable wake-up performance, enabling true power-saving mode operation with multiple power states including power-off capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves low latency and low power consumption by optimizing phase detector usage, enabling stable and quick transitions from power-saving to normal modes, with energy consumption reduced to less than 10% during power-saving operations.
Implementation Method 1
the voltage control oscillator 130 generates a recovered clock signal CLKr
Implementation Method 2
the charge pump 120 generates a control voltage Vctrl
Data Source
AI summary
A data and clock recovery circuit includes a first selecting circuit, a high speed phase detector, a low speed phase detector, a charge pump, a voltage control oscillator and a frequency divider. The high speed phase detector generates a first phase difference signal according to the first reference clock signal and a divided clock signal or according to the data signal and the divided clock signal. The low speed phase detector generates a second phase difference signal according to a second reference clock signal and the divided clock signal. The charge pump generates a control voltage according to the first phase difference signal or the second phase difference signal. The voltage control oscillator receives the control voltage, and generates a recovered clock signal. The frequency divider receives the recovered clock signal, and generates the divided clock signal.