Clock Recovery Circuit Using FIR Filters for Phase Detection
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Solution Overview
Problem
Existing clock recovery circuits require high-speed analog-to-digital converters to calculate phase differences between transmitter-side and receiver-side clock signals, leading to increased manufacturing costs and potential implementation challenges.
Innovation Solution
A clock and data recovery circuit that includes a phase interpolation circuit, a filter with FIR filters, a phase comparison circuit, and a loop filter to adjust and compare phase differences between reference and transmission-side clock signals, allowing for digital processing without the need for high-speed analog-to-digital converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-speed analog-to-digital converter is used to calculate phase difference between transmitter-side and receiver-side clock signals, then measurement precision of phase difference is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces the analog-to-digital converter-based phase difference calculation method with a digital signal processing method using FIR filters. Instead of using high-speed ADC to directly measure phase difference between clock signals, the invention uses digital filtering of data signals to extract phase information, substituting analog measurement with digital processing.
Solution Approach 2:
The patent introduces FIR filters as an intermediary mechanism to calculate phase difference. Rather than directly measuring phase difference between clock signals, the system uses filtered data signals as an intermediate representation from which phase difference can be derived, enabling lower-cost implementation.
2Measurement precision
If the sample rate of the analog-to-digital converter is increased to calculate phase difference digitally, then measurement precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the approach from increasing ADC sample rate to using digital filtering with specific tap configurations. Instead of relying on high sampling rates, the system uses FIR filters with N and N+1 taps to achieve the necessary measurement precision at lower sample rates, reducing hardware cost.
3Measurement precision
If an analog circuit is used to calculate phase difference between clock signals, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent substitutes complex analog phase difference calculation circuits with digital FIR filter-based processing. The analog circuit that would directly compare clock phases is replaced with digital filtering operations on data signals, simplifying the overall circuit architecture while maintaining measurement precision.
Data Source
AI summary
A clock and data recovery circuit includes a phase interpolation circuit that adjusts a phase of a reference clock signal generated by a reference clock generation circuit to generate a reception clock signal, a filter that performs filter processing on a data signal output from an ADC that converts an analog data signal to a digital data signal in synchronization with the clock signal, a phase comparison circuit that outputs phase difference data between a transmission-side clock signal and the reference clock signal based on an output of the filter, and a loop filter that generates phase data to be set in the phase interpolation circuit. The filter includes an FIR filter with a tap number N, and an FIR filter with a tap number N+1 that outputs a signal delayed by half a clock than the former FIR filter.