Digital Clock Recovery With Integrated Frequency Detection
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Solution Overview
Problem
Existing clock and data recovery circuits in portable devices face performance degradation due to added frequency detection circuits, leading to increased overhead and slower response times, which complicates the circuit design and changes the dynamics of clock and data recovery.
Innovation Solution
A digital frequency detection circuit is integrated within the clock and data recovery circuit, utilizing transition timing information to adjust the sampling rate of the input signal, thereby reducing the need for additional loading and allowing for lower speed components without impacting performance, and powering down when a lock is achieved to conserve power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency detection circuit is added to the input node and clock node, then frequency detection capability is improved, but loading increases and response time slows down
Solution Approach 1:
The frequency detection circuit is merged with the clock and data recovery circuit by integrating it within the existing circuit structure rather than adding it as a separate external component. This integration allows frequency detection to occur using existing circuit nodes and signals, avoiding additional loading that would slow down the circuit response.
Solution Approach 2:
The integrated frequency detection circuit serves multiple functions: it detects frequency of the input signal, assists in locking onto the frequency for clock and data recovery, and operates within the existing circuit architecture. This multi-functionality eliminates the need for separate dedicated frequency detection hardware, reducing overall circuit loading while maintaining detection capability.
2Reliability
If a frequency detection circuit is added to assist in locking onto frequency, then frequency acquisition capability is improved, but circuit complexity increases
Solution Approach 1:
The frequency detection functionality is combined with the existing clock and data recovery circuit elements. The circuit uses the same nodes and signals for both frequency detection and clock recovery operations, thereby improving frequency acquisition reliability without adding separate complex detection hardware.
Solution Approach 2:
The circuit uses its own internal signals and nodes to perform frequency detection. The input signal and clock node signals that are already present in the circuit are utilized for frequency measurement, allowing the circuit to self-diagnose and adjust without requiring external or additional specialized components.
3Measurement precision
If loading at input and clock nodes is increased by adding frequency detection circuit, then frequency detection is enabled, but sampling points of input signal change
Solution Approach 1:
The frequency detection function is merged into the existing circuit path, using the same sampling and signal paths that determine the critical sampling points. By detecting frequency within the existing signal flow rather than adding separate detection paths, the circuit maintains accurate sampling points while enabling frequency detection capability.
Data Source
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AI summary
In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.