Clock Recovery Frequency Limiting During Data Interruptions
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Solution Overview
Problem
In modern computer systems, receiver circuits that generate clock signals by recovering clock information from incoming serial data streams can experience a rapid increase in clock frequency when the data stream is interrupted, leading to potential loss of logical state and errors in circuit blocks using the clock signal.
Innovation Solution
A method is introduced that involves a measurement circuit to monitor the frequency of the clock signal and compare it to a threshold value. If the frequency exceeds the threshold, an indication signal is generated to adjust the clock frequency, preventing it from exceeding operational limits and avoiding loss of state in circuit blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the clock generator circuit recovers clock information from an incoming serial data stream, then the clock signal can be generated without external clock input, but the clock frequency may rapidly increase when the data stream is interrupted causing loss of logical state
Solution Approach 1:
The patent implements a feedback mechanism where the measured clock frequency is continuously compared against a threshold value. When the frequency exceeds the threshold, an indication signal is generated to adjust the clock frequency back to acceptable levels. This closed-loop feedback system prevents the clock frequency from rising too high during data interruptions, thereby maintaining logical state integrity while preserving clock recovery capability.
Solution Approach 2:
The patent performs preliminary frequency measurement and threshold comparison before the excessive clock frequency can cause loss of logical state. By proactively monitoring the clock frequency and generating adjustment signals in advance, the system prevents harmful frequency excursions rather than reacting after damage occurs.
2Speed
If the clock frequency is allowed to increase rapidly during data interruptions, then the clock generator responds quickly to frequency changes, but circuit blocks experience errors and loss of state
Solution Approach 1:
The patent sets up a protective mechanism in advance by establishing a threshold frequency value and continuously measuring the actual clock frequency. This cushioning approach creates a safety margin that prevents the clock frequency from reaching harmful levels during data interruptions, protecting circuit blocks from errors while allowing natural frequency variations.
3Reliability
If a measurement circuit is added to monitor clock frequency, then the clock frequency can be controlled within safe limits, but the device complexity increases
Solution Approach 1:
The measurement circuit automatically performs frequency measurement, threshold comparison, and generates adjustment signals without external intervention. The system serves itself by autonomously monitoring and correcting its own clock frequency, eliminating the need for complex external control mechanisms while maintaining reliable frequency control.
Data Source
AI summary
A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit configured to generate an equalized signal, a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit is configured to monitor a frequency of the clock signal and activate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. In response to activation of the indication signal, the clock generator circuit is configured to set the frequency of the clock signal to a particular frequency.