Clock Recovery via Frequency Prediction During Network Quiet Periods

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Solution Overview

Problem

Clock synchronization over packet networks is challenged by packet delay variations (PDV) that cause high jitter and wander, especially during high network traffic, leading to unreliable clock recovery in legacy services.

Innovation Solution

A method that utilizes quiet periods with low network traffic to train a frequency prediction unit, allowing it to predict frequency updates during high traffic periods, using an accept-rejection algorithm to select between predicted and actual values for robust clock recovery, thereby minimizing the impact of packet delay variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If timing packets are used for clock synchronization over packet networks, then cost and availability are improved, but packet delay variations cause high jitter and wander in the recovered reference clock

Engineering Contradiction:
ImprovecostVSAvoidsynchronization quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The system performs preliminary actions by detecting quiet periods in advance and training the frequency prediction unit during these low-traffic periods. This preliminary training enables the system to predict frequency updates during high-traffic periods without waiting for actual timing data, thus resolving the contradiction between using packet networks (low cost) and maintaining synchronization quality (high reliability).

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The frequency prediction unit acts as an intermediary between the timing recovery circuit and the local oscillator. During high-traffic periods when packet delay variations cause high jitter, the frequency prediction unit interpolates expected frequency updates based on trained models, mediating between the unreliable timing packets and the requirement for stable clock synchronization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If clock recovery algorithm stops during high traffic periods and enters hold-over mode, then reliability is improved by avoiding poor synchronization, but phase and frequency drift occur due to fixed value updates

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidphase and frequency stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The system maintains continuous clock recovery operation by switching between timing recovery circuit output during quiet periods and frequency prediction unit output during high-traffic periods. This continuous operation eliminates the need to stop and enter hold-over mode, while still maintaining synchronization reliability through intelligent selection based on network conditions.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system dynamically switches between two operational modes (timing recovery circuit and frequency prediction unit) based on real-time detection of network traffic conditions. This dynamic adaptation allows the system to maintain both reliability and stability by using the appropriate method for each condition, rather than stopping entirely during high-traffic periods.

Inventive Principle:
Principle #15Dynamics

3Reliability

If timing packets are filtered to reduce packet delay variation impact, then synchronization quality is improved, but device complexity increases due to additional filtering mechanisms

Engineering Contradiction:
Improvesynchronization qualityVSAvoidfiltering mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The frequency prediction unit performs self-service by automatically detecting quiet periods and training itself using timing packet data during these periods. Once trained, it autonomously predicts frequency updates during high-traffic periods without requiring complex external filtering mechanisms, thus achieving high synchronization quality while minimizing added complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP2360861B1Clock recovery method over packet switched networks based on network quiet period detection
Publication Date: 2016.04.06 MICROSEMI SEMICON
  • EP2360861B1 patent drawingFigure 1~2
  • EP2360861B1 patent drawingFigure 3~4
  • EP2360861B1 patent drawingFigure 5

AI summary

A method of recovering timing information in a packet network, involves detecting quiet periods in the packet network when network packet delay variation (PDV) is low. A frequency prediction unit is trained during the quiet periods to learn output clock variations of a timing recovery unit to permit the frequency prediction unit to predict frequency update values for a local oscillator during non quiet periods taking into account the historical output clock variations during quiet periods. The output of the frequency prediction unit is used as the active frequency update values during non quiet periods.