Reference-Less Clock Recovery for Continuous Frequency Switching
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Solution Overview
Problem
Traditional reference-less clock and data recovery circuits face challenges with increased system power consumption and burden, and unsynchronized clock signal output when data transmission frequency changes, leading to failures in clock and data recovery.
Innovation Solution
A reference-less clock and data recovery device comprising a clock and data recovery circuit, an oscillator circuit, and a processor that generates a first clock signal through synchronization in the initial frequency period and maintains output by synchronizing with an oscillating clock signal, allowing continuous clock signal generation during frequency transformation through a resynchronization procedure using a simulated preparation signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional reference-less clock and data recovery circuit is used when data transmission frequency changes, then the circuit can adapt to frequency changes, but system power consumption increases and system burden increases
Solution Approach 1:
The transmitting terminal sends a preparation signal before actual data transmission, which includes synchronization information that allows the receiving terminal to pre-establish clock and data recovery. This preliminary action enables the system to adapt to frequency changes without requiring excessive power consumption during normal operation, as the recovery circuit is already prepared and synchronized.
Solution Approach 2:
The clock and data recovery circuit dynamically adjusts its operation based on the received signal characteristics. When frequency changes are detected, the circuit transitions between different operating states efficiently, maintaining adaptability while minimizing power consumption by only activating full recovery procedures when necessary rather than continuously.
2Adaptability or versatility
If traditional reference-less clock and data recovery circuit is used when data transmission frequency changes, then the circuit can adapt to frequency changes, but the clock and data recovery circuit being in an unsynchronized state for a time period
Solution Approach 1:
The preparation signal is transmitted before data transmission to establish initial synchronization. This preliminary action ensures that when frequency changes occur, the clock and data recovery circuit is already prepared and can transition smoothly without entering an unsynchronized state, thereby maintaining reliability during frequency adaptation.
Solution Approach 2:
The system uses feedback from the received signal to continuously monitor and adjust the clock and data recovery synchronization status. When frequency changes are detected, the feedback mechanism triggers appropriate adjustments to maintain synchronization, preventing the circuit from entering an unsynchronized state and ensuring continuous reliable operation.
3Adaptability or versatility
If traditional reference-less clock and data recovery circuit is used when data transmission frequency changes, then the circuit can adapt to frequency changes, but a failure of the clock and data recovery circuit to output a clock signal during the time period
Solution Approach 1:
The preparation signal establishes preliminary clock and data recovery synchronization before data transmission begins. This ensures that when frequency changes occur during operation, the circuit maintains continuous clock signal output without failure, as the recovery mechanism is already prepared and can adapt smoothly, preventing productivity interruptions.
Solution Approach 2:
The system maintains continuous clock signal output by ensuring the clock and data recovery circuit operates without interruption during frequency changes. The preparation signal and dynamic adjustment mechanisms work together to keep the useful action of clock signal generation continuous, preventing any downtime or failure in clock output that would affect productivity.
Data Source
AI summary
A reference-less dock and data recovery device includes a CDR circuit, an oscillator circuit, and a processor. The CDR circuit is configured to generate a first clock signal through synchronization according to a data signal having a first frequency in a first time period. The oscillator circuit is configured to output an oscillating clock signal according to the first clock signal, A frequency of the oscillating clock signal is substantially identical to that of the first clock signal. The processor oversamples the data signal having a second frequency in a second time period to generate a simulated preparation signal conforming to the second frequency. The CDR circuit is configured to generate a second clock signal through synchronization according to the simulated preparation signal. Before generating the second clock signal, the CDR circuit is synchronized to the oscillating clock signal to maintain outputting of the first clock signal.