Serial-Parallel Clock Recovery With Autocorrelation Gain Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock generating circuits in high-speed data transmission systems face challenges in achieving stable high data rates due to tracking errors and jitter, particularly affected by PVT conditions, which complicates the adjustment of control loop gain and can lead to oscillatory responses.
Innovation Solution
A clock generating circuit that includes a phase detector, signal amplifying circuit, control loop, autocorrelation circuit, and gain adjusting circuit to estimate and adjust the autocorrelation value, thereby optimizing the gain for the control loop to minimize jitter and prevent oscillatory responses, using a bang-bang phase detector and digitally controlled oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control loop gain is increased to reduce tracking errors and minimize jitter, then the data transmission stability is improved, but the system may exhibit oscillatory responses under varying PVT conditions
Solution Approach 1:
The patent implements dynamic gain adjustment in the control loop by using an autocorrelation circuit to continuously monitor the phase detection signal and adaptively adjust the loop gain based on signal characteristics. This allows the system to maintain optimal tracking performance while preventing oscillatory behavior under varying PVT conditions, resolving the contradiction between reliability and stability.
Solution Approach 2:
The patent employs a feedback mechanism where the autocorrelation circuit analyzes the phase detection signal and feeds back adjusted gain control to the signal amplifying circuit. This closed-loop feedback system automatically adjusts the control loop gain to maintain stability while minimizing jitter and tracking errors, addressing both reliability and stability requirements.
2Productivity
If the data rate is increased to improve information processing speed, then the bandwidth is increased, but the tracking errors and jitter increase making stable transmission difficult to achieve
Solution Approach 1:
The patent changes the gain parameter of the control loop dynamically based on the data rate and signal characteristics. By adjusting the loop gain in response to varying data rates and PVT conditions, the system maintains stable transmission even at high speeds of 25 Gbps or 50 Gbps, resolving the contradiction between productivity and reliability.
Solution Approach 2:
The system dynamically adapts the control loop characteristics to match the operating conditions. The autocorrelation circuit continuously monitors signal quality and adjusts the loop gain accordingly, enabling stable high-speed transmission by optimizing the control parameters in real-time rather than using fixed parameters.
Data Source
AI summary
A serial-parallel conversion circuit includes: a phase detector that outputs a first phase detection signal indicating whether a phase of a clock signal is advance or behind, a signal amplifying circuit that amplifies the first phase detection signal with a gain so as to output a second phase detection signal; a control loop that adjusts the phase of the clock signal based on the second phase detection signal; an autocorrelation circuit that generates an autocorrelation value based on the first phase detection signal and a set delay amount, and outputs an autocorrelation signal indicating the autocorrelation value; a gain adjusting circuit that adjusts the gain in such a manner that the autocorrelation value matches a target correlation value; and a delay-amount determination circuit that sets a delay amount corresponding to a peak value of an obtained autocorrelation value obtained when the autocorrelation value changes in an oscillatory manner.