Clock Recovery Circuit Timing for Pre-Cursor ISI Eye Opening
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Solution Overview
Problem
Clock and data recovery circuits face challenges in generating a sampling clock signal at optimal timing due to intersymbol interference (ISI), particularly pre-cursor ISI, which affects the recovery of digital data from analog signals.
Innovation Solution
A clock and data recovery circuit that includes an equalizer, subtractor, decision feedback equalization unit, clock signal generator, and controller, which generates sampling clock signals and adjusts reference data levels and decision feedback equalization coefficients based on error data to maximize eye opening by considering pre-cursor ISI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR circuit is used without considering pre-cursor ISI, then the circuit structure is simple, but the sampling clock timing cannot be optimized due to intersymbol interference
Solution Approach 1:
The equalization process is segmented into feed-forward equalization (FFE) and decision feedback equalization (DFE) components. The FFE handles pre-cursor ISI while the DFE handles post-cursor ISI, allowing each segment to specialize in specific types of interference without requiring complete redesign of the entire equalization system.
Solution Approach 2:
The feed-forward equalization unit performs preliminary equalization by compensating for pre-cursor ISI before the decision feedback equalization unit processes the signal. This preliminary action removes the harmful pre-cursor interference early in the signal processing chain, improving subsequent detection accuracy.
Solution Approach 3:
The decision feedback equalization unit uses feedback from previously decided data symbols to compensate for post-cursor ISI. The controller adjusts the DFE coefficients based on error signals, creating a closed-loop feedback system that continuously optimizes equalization performance.
2Measurement precision
If multiple sampling clock signals are generated for DFE operation, then pre-cursor ISI can be considered, but the clock signal generation complexity increases
Solution Approach 1:
Multiple sampling clock signals are generated periodically at different time instances corresponding to different symbol periods. The first sampling clock signal is used for FFE operation while the second sampling clock signal is used for DFE operation, creating a periodic sampling pattern that captures both pre-cursor and post-cursor information.
Solution Approach 2:
The problem is extended from a single time dimension to multiple time dimensions by introducing multiple sampling clock signals with different phases. This dimensional extension allows simultaneous observation of signal characteristics at different time points, enabling comprehensive ISI compensation.
3Reliability
If decision feedback equalization is implemented, then post-cursor ISI can be compensated, but the equalization process becomes more complex
Solution Approach 1:
The feed-forward equalization unit performs preliminary equalization by compensating for pre-cursor ISI before the decision feedback equalization unit processes the signal. This preliminary action removes the harmful pre-cursor interference early in the signal processing chain, improving subsequent detection accuracy.
Solution Approach 2:
The decision feedback equalization unit uses feedback from previously decided data symbols to compensate for post-cursor ISI. The controller adjusts the DFE coefficients based on error signals, creating a closed-loop feedback system that continuously optimizes equalization performance.
Data Source
AI summary
A clock and data recovery circuit includes an equalizer configured to equalize an input signal to generate an equalization input signal, a subtractor configured to subtract a decision feedback equalization signal from the equalization input signal to generate a sampling input signal, a decision feedback equalization unit configured to generate first digital data corresponding to the sampling input signal in response to a first sampling clock signal, generate second digital data corresponding to the sampling input signal in response to a second sampling clock signal having a predetermined time difference with the first sampling clock signal, and compare the sampling input signal and a reference data level. A controller is configured to adjust the reference data level, determine a maximum eye opening and adjust a sample timing based on the reference data level.