Clock Recovery Circuit With Configurable Delay for Switching Jitter

The patent segments the clock recovery process into multiple independent differential receivers (first, second, third receivers) that each process different differential signal pairs. This segmentation allows the system to handle high data rates by distributing the processing load across multiple receivers, thereby maintaining signal integrity while improving data communication efficiency.

The patent introduces an intermediary clock recovery circuit that generates a clock signal based on zero-cross detections from multiple differential receivers. This intermediary clock signal serves as a mediator to synchronize the sampling of high-speed data signals, enabling reliable clock recovery even at high data rates where direct sampling would be affected by switching jitter.

The patent merges the outputs of multiple differential receivers by detecting zero-cross points across all receivers and combining these detections to generate a single clock signal. This merging approach improves clock recovery accuracy by using multiple signal sources, while the parallel processing architecture enables support for high data rates without being limited by jitter in any single receiver path.

The patent uses excessive action by implementing more differential receivers than the minimum required (using three differential receivers instead of the theoretical minimum of two). This provides redundant zero-cross detection points, improving clock recovery accuracy through multiple measurements while the parallel architecture maintains high data rate capability.

The patent implements universal differential receiver circuits that can process multiple differential signal pairs using the same hardware architecture. Each receiver is designed to be multi-functional, capable of handling different signal combinations (e.g., signal A relative to B, C, and D). This universality improves clock recovery reliability through multiple processing paths while minimizing device complexity by reusing the same circuit design patterns.

The patent changes the operational parameters of the differential receivers by configuring them to process different differential signal combinations from the same set of differential signals. By changing which signal pairs each receiver monitors (e.g., A-B, A-C, A-D), the system achieves improved clock recovery reliability without adding proportional complexity, as the same receiver type is reconfigured for different parameter combinations.