Multi-Phase Clock Data Recovery for Jitter-Tolerant Sampling
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Solution Overview
Problem
Conventional clock data recovery circuits require complex designs and circuits to manage jitter, leading to increased design difficulties and costs.
Innovation Solution
A clock data recovery circuit that includes a phase blender, phase detector, data sampling position detector, and data selector, which generates multiple clock signals with different phases to sample data signals and select correct data based on phase states, improving jitter tolerance with a simple structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock data recovery circuits are used to overcome jitter, then data transmission correctness can be maintained, but design difficulty and circuit cost increase
Solution Approach 1:
The circuit divides the single sampling operation into multiple parallel sampling paths, each sampling at different phase positions (first, second, third, fourth sampled data). This segmentation allows the system to handle jitter by selecting the correct sample without requiring complex adjustment algorithms, thus maintaining reliability while simplifying the overall control logic.
Solution Approach 2:
The circuit performs preliminary sampling at multiple phase positions before the final data selection. By pre-sampling the data signal at four different phase points (CK1, CK2, CK3, CK4), the system prepares multiple candidate values in advance, allowing the selector to choose the correct one based on phase state signals without complex real-time adjustment.
2Adaptability or versatility
If multiple clock signals with different phases are used for sampling, then jitter tolerance is improved, but circuit structure becomes more complex
Solution Approach 1:
The circuit merges multiple sampling operations into a unified structure where four parallel sampling paths (using clock signals CK1-CK4 with different phases) are combined through a selection mechanism. The phase blender generates multiple phase-shifted clocks, and the data selector combines the sampled results, achieving high jitter tolerance through a systematic yet compact integrated design.
Solution Approach 2:
The sampling circuit is designed to be universal by implementing multiple phase sampling paths that can handle various jitter conditions. The same basic sampling structure is replicated four times with different phase shifts, creating a multi-functional system that adapts to different jitter scenarios without requiring separate specialized circuits for each case.
3Measurement precision
If complex algorithms are used for adjustment between data signal and clock signal, then data correctness is improved, but design difficulty increases
Solution Approach 1:
The circuit replaces complex algorithmic adjustments with a straightforward phase-based selection mechanism. Instead of using sophisticated digital signal processing algorithms to detect and correct timing offsets, the system uses phase state signals (indicating leading/lagging states) to directly select the appropriate pre-sampled data, substituting mechanical/control complexity with a simpler signal-based selection approach.
Data Source
AI summary
A clock data recovery circuit including a phase blender, a phase detector, a data sampling position detector and a data selector is provided. The phase blender generates a third clock signal and a fourth clock signal according to a first clock signal and a second clock signal. The phase detector samples a data signal according to the first and second clock signals to generate first sampled data, second sampled data and a phase state signal. The data sampling position detector samples the data signal according to the third and fourth clock signals to generate third sampled data, fourth sampled data and a control signal. The data selector generates output data according to the control signal and the phase state signal.