Clock Recovery Circuit Using Pulse-Triggered Loop Interruption
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Solution Overview
Problem
Existing clock recovery methods for high-speed communication, such as C-PHY, face limitations in reducing delay time, leading to decreased accuracy and efficiency of clock signal recovery, as well as increased circuit area and power consumption.
Innovation Solution
A signal receiving circuit that employs a clock signal recovery unit with a loop interruption circuit and a delay circuit, utilizing differential signals and pulses to generate recovery clock signals and delay signals, thereby optimizing clock recovery in high-speed communication environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-rate clock recovery method is used, then one rising edge corresponds to each received symbol, but additional time delay is needed and maximum operating speed is limited
Solution Approach 1:
The patent uses periodic pulse signals generated from differential signal edges to trigger clock recovery at regular intervals, replacing the continuous full-rate clock generation. This periodic triggering eliminates the need for additional delay circuits while maintaining synchronization accuracy.
Solution Approach 2:
The patent extracts only the essential edge information from differential signals to generate trigger pulses, removing the need for complex delay circuits required in full-rate methods. This extraction approach maintains clock accuracy while reducing operational delays.
2Speed
If half-rate clock recovery method is used, then both rising and falling edges are used, but delay time reduction is limited and accuracy decreases at high speeds
Solution Approach 1:
The patent segments the clock recovery process into independent pulse generation stages, where each differential signal pair (AB, BC, CA) generates its own pulse independently. This segmentation allows precise timing control for each edge transition, maintaining accuracy even at high speeds where half-rate methods fail.
3Measurement precision
If additional delay circuits are added to generate falling edges, then full-rate clock recovery is achieved, but circuit area and power consumption increase
Solution Approach 1:
The patent merges the clock recovery function with the existing differential signal processing circuitry. The same pulse generators used for data recovery are also used for clock recovery, eliminating the need for separate delay circuits and reducing overall circuit area.
Solution Approach 2:
The pulse generators are designed to serve dual purposes: generating trigger signals for data recovery and generating clock signals for synchronization. This multi-functionality eliminates redundant circuits and reduces both area and power consumption.
4Measurement precision
If additional delay circuits are added to generate falling edges, then full-rate clock recovery is achieved, but power consumption increases
Solution Approach 1:
The patent merges the clock recovery function with the existing differential signal processing circuitry. The same pulse generators used for data recovery are also used for clock recovery, eliminating the need for separate delay circuits and reducing overall circuit area.
Solution Approach 2:
The pulse generators are designed to serve dual purposes: generating trigger signals for data recovery and generating clock signals for synchronization. This multi-functionality eliminates redundant circuits and reduces both area and power consumption.
Data Source
AI summary
A signal receiving circuit includes first to third pulse generators; and a clock signal recovery unit 100 for generating a recovery clock signal RCLK and a recovery clock delay signal RCLKD, which is a signal obtained by delaying the recovery clock signal as much as a first delay time, using at least one of pulses including a first pulse, a second pulse, a third pulse, and first to third inversion pulses, wherein the clock signal recovery unit includes: a loop interruption circuit including an input node and an output node and turned on and off by at least one of the pulses; and a delay circuit having an input terminal connected to the output node and an output terminal connected to the input node. A signal value of the input node and a signal value of the output node are in an inverse relationship.