Clock Data Recovery Using Predictive Missing-Edge Insertion
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Solution Overview
Problem
Conventional software PLLs for clock data recovery face challenges in real-time processing due to processing time delays, which can destabilize the phase-locked loop and limit the minimal analysable bit period, making them unsuitable for high-speed data streams.
Innovation Solution
The method relocates the handling of missing edges outside the phase-locked loop, using a predictive approach to detect and fill missing edges based on a 'front clock' signal, simplifying the PLL structure and enabling parallel processing, thereby reducing the minimal analysable bit period and increasing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional software PLL processes data edges sequentially within the loop, then clock signal can be recovered, but processing time delays increase and destabilize the phase-locked loop
Solution Approach 1:
The patent segments the missing edge detection process from the main PLL loop by introducing a front clock signal that operates independently. The front clock predicts clock edges and enables parallel processing of data edges, separating the time-consuming detection task from the critical PLL feedback path, thus reducing processing delays while maintaining stability
Solution Approach 2:
The front clock signal performs preliminary action by predicting future clock edges before the main PLL processes them. This advance prediction allows the system to prepare for upcoming edges, reducing the critical processing time within the PLL loop and preventing destabilization delays
2Manufacturing precision
If conventional software PLL handles all data edges within the loop, then complete edge processing is achieved, but minimal analysable bit period increases
Solution Approach 1:
The patent extracts the missing edge detection function from the main PLL loop and places it in the parallel front clock path. This extraction allows the PLL to process only essential feedback while the front clock handles predictive detection, reducing the minimal bit period requirement and increasing throughput for high-speed data streams
3Device complexity
If sequential processing is used within the PLL loop, then processing complexity is managed, but throughput decreases
Solution Approach 1:
The patent introduces a temporal dimension by using the front clock to predict future edges ahead of the main PLL processing. This creates a parallel processing dimension where edge detection occurs simultaneously with PLL operation, increasing throughput without significantly increasing overall system complexity
Data Source
AI summary
A method for the recovery of a clock signal from a data signal, wherein the edges of the data signal and the clock signal are each presented by an ordered sequence of timing points, comprising determining missing edges in the sequence of data-signal edges, inserting new data-signal edges (Dx) into the sequence of data-signal edges to obtain a completed sequence of data-signal edges, and recovering the clock signal from the completed sequence of data-signal edges. The detection of missing edges in the sequence of data-signal edges is based on a prediction of the clock signal (FRONT CLOCK).