Reference-Less Clock Recovery Circuit for Multi-Format Data Signals
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits require a reference clock signal, increasing complexity and cost, and are limited to recovering clock signals from Non-Return to Zero (NRZ) data signals, failing to accommodate other data signal formats.
Innovation Solution
A reference-less CDR circuit that uses sampling circuits and a control circuit to generate control signals for adjusting the frequency of a clock signal based on an input data signal, allowing recovery of clock signals from any data signal format, including NRZ, PAM, and PAM4, without the need for a separate reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference clock signal is used in the FLL circuit, then the clock recovery operation can be performed, but the complexity and cost of the circuit increases
Solution Approach 1:
The patent removes the reference clock signal requirement from the FLL circuit, extracting this external dependency to create a reference-less implementation. The circuit now generates its own clock signal internally without needing an external reference, thereby reducing circuit complexity and cost while maintaining clock recovery functionality.
Solution Approach 2:
The FLL circuit is modified to be self-sufficient by eliminating the need for an external reference clock signal. The circuit generates and maintains its own clock signal through internal mechanisms, making it autonomous and reducing system complexity.
2Reliability
If D-type flip flops are used to sample the clock signal, then the clock signal can be recovered, but the input data signal is limited to NRZ format only
Solution Approach 1:
The patent enhances the universality of the CDR circuit by modifying it to accept multiple data signal formats (NRZ, PAM4, and others) instead of being limited to NRZ only. The circuit incorporates detection mechanisms that can identify different signal formats and adjust its operation accordingly, making it applicable to a broader range of communication standards and applications.
Solution Approach 2:
The circuit employs dynamic detection and adaptation mechanisms that allow it to automatically adjust its operation based on the detected data signal format. This dynamic capability enables the circuit to maintain reliable clock recovery across different signal formats without requiring manual configuration or separate dedicated circuits for each format.
Data Source
AI summary
An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.