Clock Recovery Circuit Using Multi-Phase Detection Under Data Distortion
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Solution Overview
Problem
Existing clock and data recovery circuits face challenges in maintaining stable operation due to data distortion, particularly from factors like jitter and skew, leading to inaccurate phase and frequency detection.
Innovation Solution
An integrated circuit with a phase shifted data generation circuit, synchronization circuit, and control signal generation circuit that generates phase and frequency control signals based on multiple clock signals with different phases, allowing for stable detection even in distorted data conditions, without the need for a separate frequency locking loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional clock and data recovery circuit is used, then the system can recover clock signals, but the detection accuracy deteriorates due to data distortion from jitter and skew
Solution Approach 1:
The detection process is segmented into multiple sampling operations with different phase shifts (0°, 90°, 180°, 270°). Instead of relying on a single sampling point that is vulnerable to distortion, the circuit divides the detection into multiple independent sampling instances, each capturing data at different phase positions. This segmentation allows the system to identify and compensate for distortion effects by comparing results across multiple samples.
Solution Approach 2:
The circuit employs periodic sampling at multiple phase intervals throughout the clock cycle. By systematically sampling at 0°, 90°, 180°, and 270° phases in a repeating sequence, the system captures the periodic nature of the clock signal while identifying deviations caused by jitter and skew. This periodic multi-phase sampling enables accurate frequency and phase detection despite instantaneous distortions.
2Reliability
If multiple sampling operations with different phase shifts are performed, then detection stability improves, but the system complexity increases
Solution Approach 1:
Multiple sampling operations with different phase shifts are merged into a unified detection framework. The phase shifted data generation circuit combines several sampling paths that operate in parallel, and the control signal generation circuit integrates their outputs through logical operations. This merging allows the system to achieve stable detection under distortion while maintaining a compact circuit structure that does not require separate independent detection paths for each phase.
Solution Approach 2:
The detection circuit is designed with multi-functionality to handle both phase and frequency detection using the same multi-phase sampling infrastructure. The same sampling circuit that captures data at multiple phases also generates the information needed for both phase error detection and frequency measurement. This universal approach eliminates the need for separate dedicated circuits for different detection functions, reducing overall system complexity.
3Measurement precision
If a separate frequency locking loop is added to improve frequency tracking, then frequency accuracy improves, but the system complexity and operation time increase
Solution Approach 1:
Phase detection and frequency detection functions are merged into a single integrated detection process. The multi-phase sampling circuit simultaneously provides information for both phase error calculation and frequency measurement. By combining these functions, the system achieves accurate frequency tracking without requiring a separate frequency locking loop, thereby reducing circuit complexity and operational overhead while maintaining high detection precision.
Data Source
AI summary
An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.