Clock Recovery Circuits for Low-Frequency Multiphase Power Switching
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Solution Overview
Problem
In multiphase switched mode power conversion systems, the phase-locked loop (PLL) fails to lock at low clock pulse frequencies during pulse-frequency modulation (PFM) mode due to parasitic capacitances, leading to potential missed switching events and reduced efficiency.
Innovation Solution
Implementing clock recovery circuits that interleave master and slave clock phases at equal intervals, allowing the master device to generate and determine the timing of clock pulses, even at low frequencies, thereby maintaining interleaved switching behavior between master and slave phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked loop (PLL) is used to synchronize power switching operations, then clock signal synchronization is achieved, but the PLL fails to lock at low clock pulse frequencies due to parasitic capacitances
Solution Approach 1:
The patent introduces a clock recovery circuit as an intermediary between the master device and slave devices. This circuit receives clock pulses from the master device, recovers the clock signal independently of the PLL, and generates synchronized clock signals for slave devices. The clock recovery circuit uses a counter and logic circuits to reconstruct the clock signal at equal intervals, bypassing the PLL locking issue at low frequencies while maintaining synchronization across the multiphase system.
2Stability of the object's composition
If master device generates and determines timing of clock pulses, then interleaved switching behavior is maintained at low frequencies, but device complexity increases due to clock recovery circuits
Solution Approach 1:
The patent divides the clock synchronization function into separate segments: the master device generates clock pulses, the clock recovery circuit recovers and distributes them, and slave devices execute switching based on recovered clocks. This segmentation allows each component to perform its specific function independently, maintaining stable interleaved switching behavior while distributing the complexity across multiple dedicated circuits rather than requiring a complex unified synchronization system.
Data Source
AI summary
Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.