Clock and Data Recovery Reset Logic for Fast Noise Rejection
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Solution Overview
Problem
Existing clock and data recovery systems face challenges in quickly acquiring phase lock and tracking signals, especially in the presence of noise, due to variations in data rates and noise interference, which can lead to prolonged acquisition times and reduced system efficiency.
Innovation Solution
A system comprising a signal processing circuit that acquires phase lock and tracks input signals in two modes, with a reset circuit that counts cycles of a clock signal between signal edges to generate a count and resets the processing circuit when the count is outside a predetermined range, effectively distinguishing between noise-induced zero crossings and actual data signals to facilitate fast acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the signal processing circuit operates in acquisition mode to quickly lock onto the input signal, then the acquisition time is reduced, but the system may mistakenly lock onto noise-induced zero crossings instead of actual data signals
Solution Approach 1:
A range circuit is introduced as an intermediary component between the signal processing circuit and the reset circuit. This range circuit monitors the count value generated by counting clock cycles between signal edges and only permits phase lock when the count falls within a predetermined valid range, thereby preventing false locking onto noise while maintaining fast acquisition capability
Solution Approach 2:
The system implements feedback through the reset circuit that continuously monitors the count value and provides reset signals to the signal processing circuit when the count exceeds the valid range. This feedback mechanism ensures that the system maintains reliable phase lock by correcting deviations caused by noise interference
2Measurement precision
If the system uses a high-frequency oversampled clock to improve tracking accuracy, then the measurement precision is improved, but the complexity of distinguishing noise from actual signals increases
Solution Approach 1:
The system changes the parameter of clock frequency by using an oversampled high-frequency clock for internal operations while introducing a range parameter (predetermined valid range) that filters out noise-induced variations. This allows high-precision measurement while simplifying noise discrimination through parameter-based validation
3Reliability
If the reset circuit continuously monitors and resets the signal processing circuit, then the system reliability is improved by preventing false phase lock, but the processing time is increased due to additional counting and validation operations
Solution Approach 1:
The reset circuit performs partial monitoring by only checking whether the count value falls within the predetermined valid range, rather than performing exhaustive analysis. This partial action approach maintains reliability by preventing obvious false locks while minimizing additional processing time through simplified validation logic
Data Source
AI summary
Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.