Clock Recovery Circuit Offset Control for Stable Phase Locking
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in accurately recovering clock signals and data from received signals due to inter-symbol interference and phase locking issues, particularly in high-speed serial communication systems like SD™ and PCIe™, where false convergence points can lead to erroneous phase locking.
Innovation Solution
A clock data recovery circuit with a Mueller-Muller baud-rate phase detector and a loop filter that calculates phase correction amounts, combined with an offset control mechanism to gradually adjust an initial offset to zero, ensuring accurate phase locking of the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional phase detector is used in the clock data recovery circuit, then the circuit can operate with simpler structure, but false convergence points occur leading to erroneous phase locking
Solution Approach 1:
The patent implements a feedback mechanism where the loop filter continuously monitors the phase detection output and adjusts the clock signal phase accordingly. The phase detector output feeds back to the loop filter, which generates correction signals to eliminate phase errors, ensuring accurate phase locking while maintaining system stability through controlled feedback loops.
Solution Approach 2:
The loop filter acts as an intermediary between the phase detector and the clock signal source. It processes the phase detection output, smooths fluctuations, and generates appropriate control signals for phase correction, thereby preventing false convergence points from causing erroneous phase locking while maintaining overall system functionality.
2Speed
If the offset is adjusted rapidly to correct phase errors, then phase locking speed is improved, but system stability deteriorates due to oscillations
Solution Approach 1:
The patent implements dynamic offset adjustment where the loop filter adapts its response characteristics based on the current phase error conditions. The filter dynamically modifies its gain and time constants to balance between rapid convergence when large phase errors exist and stable operation when approaching the locked state, preventing oscillations while maintaining fast locking speed.
Solution Approach 2:
The loop filter changes its operational parameters (gain, time constant) based on the phase error magnitude and system state. When phase errors are large, the filter allows faster correction; when errors are small, it reduces gain to prevent overshoot and oscillations, thereby achieving both fast phase locking and system stability through parameter adaptation.
Data Source
AI summary
A semiconductor integrated circuit includes a converter converting an analog signal into a digital signal based on a clock signal; a comparator determining values of data based on the digital signal; a recovery circuit recovering the clock signal based on the digital signal and the data; and a control circuit. The recovery circuit includes a phase detector calculating a sum of a first value and offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and a loop filter calculating a correction amount of the phase of the clock signal based on the sum. The control circuit is configured to gradually change the offset from a second value to zero after the second value is added as the offset.