Clock Recovery Offset Control Under Jitter and Intersymbol Interference
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Solution Overview
Problem
Existing clock/data recovery devices struggle to reliably recover clock signals and data when transmitter clock jitter and intersymbol interference are high, leading to instability in signal recovery.
Innovation Solution
A clock/data recovery device comprising a sampler, detector, offset determination part, and clock output part, which adjusts the phase and offset of clock signals to match the data transition time distribution, using two loops to synchronize the clock signals with the input digital signal and correct the offset based on the phase relationship and data patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock/data recovery devices detect data at three timings (start, middle, end of stability period) and adjust timings to match, then clock signal recovery is achieved, but the device cannot stably recover signals when transmitter clock jitter and intersymbol interference are high
Solution Approach 1:
The patent divides the data stability period into three distinct detection timings (first timing near start, second timing near end, third timing at middle) and processes each timing separately. This segmentation allows the device to capture data transition characteristics at multiple points, enabling more robust clock recovery even when jitter and interference cause variations in transition timing.
Solution Approach 2:
The device uses feedback mechanisms where the detected data at three timings is compared and used to adjust the clock signal timing. The bit error rate detection and timing adjustment based on matched filter outputs create a closed-loop system that continuously refines clock recovery accuracy, improving stability under high jitter conditions.
2Measurement precision
If the device adjusts timing to equate bit error rates at first and second timings within start setting range, then clock signal recovery is achieved, but reliability deteriorates when transmitter clock jitter and intersymbol interference are high
Solution Approach 1:
The patent implements dynamic timing adjustment where the detection timings are not fixed but are adaptively adjusted based on the detected data characteristics and bit error rates. The device dynamically modifies the first and second timings within the start setting range to maintain optimal detection accuracy, allowing the system to adapt to varying jitter and interference conditions rather than relying on static timing settings.
Data Source
AI summary
A clock/data recovery device 1 comprises a sampler 10, a detector 20, an offset determination part 30, a clock output part 40, and a DA converter 50. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (±Voff) added in the sampler 10 is adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n−1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n−1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.