Clock Recovery via Dynamic Packet Rate Adjustment
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Solution Overview
Problem
Current methods for clock recovery in Time Division Multiplex (TDM) signals over packet networks face challenges due to packet delay variation (PDV), leading to synchronization quality issues and dependency on convergence time and latency, particularly in adaptive PLL-based methods.
Innovation Solution
A method and node for clock recovery in packet networks that adjust the rate of encapsulation packet generation based on a counter value compared to threshold values, allowing for dynamic payload size adjustment and timestamp-based corrections, enabling accurate clock recovery without requiring external network reference clocks or special network upgrades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If adaptive PLL-based clock recovery methods are used, then clock recovery is achieved, but convergence time and latency increase
Solution Approach 1:
Instead of adjusting the local clock frequency to match the incoming TDM signal (traditional adaptive PLL approach), the invention inverts the approach by adjusting the packet generation rate at the egress side to match the incoming signal characteristics. This reverses the conventional wisdom and eliminates the convergence time issue since no frequency locking is required.
Solution Approach 2:
The invention dynamically adjusts the packet generation rate based on real-time packet delay variation measurements. By continuously monitoring PDV and adapting the egress packet rate accordingly, the system achieves clock recovery without the static convergence time limitations of traditional PLL methods.
2Stability of the object's composition
If jitter buffer is used to mitigate PDV, then packet delay variation is reduced, but precise rate control for clock recovery is lost
Solution Approach 1:
The invention implements a feedback mechanism where the egress Provider Edge continuously monitors packet delay variation and uses this information to adjust the packet generation rate. This closed-loop feedback system maintains both PDV mitigation and precise clock recovery capability simultaneously.
Solution Approach 2:
The system changes the packet generation rate parameter dynamically based on observed PDV conditions. By adjusting this critical parameter in real-time, the system maintains synchronization accuracy while still benefiting from jitter buffer-based PDV mitigation.
3Reliability
If network synchronous methods are used, then synchronization quality improves, but reference timing distribution complexity increases
Solution Approach 1:
The invention extracts the timing recovery function from the complex network synchronous distribution system. By implementing clock recovery locally at the egress Provider Edge based on observed PDV, the system eliminates dependency on complex reference timing distribution while maintaining high synchronization quality.
Solution Approach 2:
The egress Provider Edge performs self-synchronized clock recovery by locally measuring PDV and adjusting its own packet generation rate accordingly. This self-service approach eliminates the need for complex external reference timing distribution systems.
Data Source
AI summary
A method of clock recovery of Time Division Multiplex signal in a packet network, wherein a first Provider Edge receives a timing message from a second Provider Edge and upon reception of said timing message a counter of said first Provider Edge is increased. The first Provider Edge sends to the second Provider Edge encapsulated Time Division Multiplex packet traffic and each packet sent to the second Provider Edge causes the counter to decrease. The first Provider Edge compares value of the counter with an Upper Threshold value and with a Low Threshold value and increases a rate of generation of the encapsulation packets if the counter is above said Upper Threshold or reduces the rate of generation of the encapsulation packets if the counter is below said Low Threshold.