Clock Recovery via Partial Timing Interpolation for Low-Latency PAM-n
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Solution Overview
Problem
Current clock data recovery methods for high data rate serial signals, such as PAM-n signals, face challenges in achieving real-time recovery with low latency and computational efficiency, particularly when using phase-locked loops or blind oversampling techniques.
Innovation Solution
A clock recovery method that first determines partial clock timings and symbol periods from data signal edge timings, using histograms to refine partial clock timing hypotheses and then interpolates full clock timings with reduced computational effort, employing both hardware and software modules for efficient processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked loop based clock data recovery is used, then clock signal recovery is achieved, but latency increases and real-time processing capability deteriorates
Solution Approach 1:
The patent segments the clock recovery process into two distinct stages: (1) partial clock recovery at a reduced sampling rate to capture essential timing information, and (2) full clock reconstruction by interpolating between partial clock timings. This segmentation allows the system to avoid the high latency of traditional PLL approaches while maintaining reliable clock recovery, as the partial clock timings provide sufficient reference points for reconstruction without requiring continuous high-rate sampling.
Solution Approach 2:
The patent applies partial action by recovering only a subset of clock timings (partial clock timings) at a reduced sampling rate rather than recovering all clock timings at the full data rate. This partial recovery is sufficient because the clock signal can be reconstructed by interpolating between these partial timings, thereby reducing computational load and latency while maintaining accuracy.
2Reliability
If blind oversampling at high sampling rate is used, then clock recovery capability is improved, but computational complexity and resource consumption increase
Solution Approach 1:
The patent recovers clock timings at only a partial set of points (partial clock timings) rather than at every clock cycle. By sampling at a reduced rate and recovering timing information only at these partial points, the computational complexity is significantly reduced while the full clock signal can be reconstructed through interpolation between these partial timings.
Solution Approach 2:
The clock recovery process is divided into two segments: (1) partial clock recovery at reduced sampling rate requiring minimal computation, and (2) clock reconstruction through interpolation. This segmentation reduces the computational burden compared to blind oversampling which would require processing every sample at high rate, while still achieving accurate clock recovery.
3Reliability
If direct recovery of all clock timings from data edges is performed, then complete clock signal is obtained, but computational effort increases significantly
Solution Approach 1:
The patent determines clock timings only at partial clock points rather than at every clock cycle. This partial determination is sufficient because the complete clock signal can be reconstructed by interpolating between these partial timings, thereby achieving the same accuracy with significantly reduced computational effort.
Solution Approach 2:
The patent performs preliminary partial clock recovery at reduced sampling rate to obtain key timing reference points. These partial clock timings serve as preliminary results that facilitate the subsequent reconstruction of the full clock signal, reducing the overall computational effort required compared to directly recovering all clock timings.
Data Source
AI summary
A clock recovery method for recovering a clock signal from a data signal is described, wherein the data signal comprises a symbol sequence. The clock recovery method comprises the following steps: The data signal is received. At least two partial clock timings of a partial clock signal that is based on the data signal are determined. The number of symbols between the at least two partial clock timings is determined. Clock timings of the clock signal are determined based on the at least two partial clock timings and the number of symbols. Further, a clock recovery module is described.