Clock Recovery Loop for Pattern-Distorted Data Signals
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Solution Overview
Problem
Conventional clock and data recovery (CDR) systems are intolerant to deterministic distortion, particularly pattern-based distortions like Periodically Distorted Unit Interval (PDUI), which affects signal processing accuracy due to sub-optimal clock signal placement.
Innovation Solution
A system comprising a phase detector, filters, a pattern error detector, and a controlled oscillator that generates a clock signal independent of transition density, using phase and pattern error signals to adjust the clock signal placement, ensuring optimal distortion tolerance by positioning clock edges at the center of data transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR systems are used, then the system is simple and easy to manufacture, but the system is intolerant to deterministic distortion such as PDUI
Solution Approach 1:
The CDR system is segmented into two independent control loops: a phase detector loop for non-deterministic distortion (jitter) and a pattern error detector loop for deterministic distortion (PDUI). Each loop processes specific error signals and generates separate control signals that are combined to drive the controlled oscillator, allowing specialized handling of different distortion types without requiring a complete system redesign
Solution Approach 2:
The controlled oscillator serves multiple functions by responding to both the phase control signal and the pattern error control signal simultaneously. This multi-functionality allows a single oscillator to correct both jitter and PDUI effects, eliminating the need for separate oscillators for each distortion type while maintaining system reliability
2Measurement precision
If conventional CDR systems are used, then the device complexity is low, but the measurement precision of clock signal placement deteriorates
Solution Approach 1:
The pattern error detector acts as an intermediary component that specifically measures deterministic distortion (PDUI) effects on the clock signal. It generates a pattern error signal that quantifies the deviation of clock edges from optimal sampling positions, enabling precise measurement and correction of clock placement accuracy without requiring complex overall system architecture
3Measurement precision
If the clock signal is generated without pattern error correction, then the system is simpler to operate, but the sampling accuracy deteriorates under deterministic distortion
Solution Approach 1:
The pattern error detector continuously monitors the clock signal for deterministic distortion and generates a pattern error signal that feeds back to the controlled oscillator. This feedback mechanism automatically adjusts the clock signal placement in real-time to compensate for PDUI effects, maintaining high sampling accuracy without requiring manual intervention or complex operational procedures
Data Source
AI summary
A system can include a phase detector configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal.