Clock Recovery Using PCR Inter-Arrival Time Averaging

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Solution Overview

Problem

Conventional digital video communication systems face challenges in clock recovery due to frequency differences between transmitter and receiver system clocks, significant jitter introduced by communication channels, and delays in Program Clock Reference (PCR) packet arrival, leading to synchronization issues and problems like color loss and audio dropouts, especially in worst-case channel conditions.

Innovation Solution

A low-complexity and low-cost clock recovery system that computes the average arrival time of PCR packets, synchronizes it with the system clock frequency, and uses a controlled clock period difference computation element with an error correction device to minimize errors, predicting an average PCR difference value at regular intervals to correct the voltage-controlled oscillator (VCXO) and maintain synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional clock recovery methods are used, then synchronization can be maintained under normal conditions, but the system fails to maintain synchronization under worst-case channel conditions (1/4 guard interval, channel fading, low carrier-to-noise ratio)

Engineering Contradiction:

Improvesynchronization reliabilityVSAvoidadaptability to channel conditions

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The system performs preliminary estimation of the average PCR arrival time difference before actual synchronization occurs. By predicting the average inter-arrival time of PCR packets in advance and using this prediction to pre-adjust the system clock, the system prepares for synchronization challenges before they fully manifest, thereby improving reliability under worst-case conditions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system continuously monitors actual PCR packet arrival times and compares them with the estimated average arrival time. This feedback mechanism allows the system to detect deviations caused by channel conditions and adjust the system clock accordingly, maintaining synchronization reliability despite varying channel quality.

Inventive Principle:

Principle #23Feedback

2Measurement precision

If complex clock recovery apparatus is used, then clock recovery accuracy can be improved, but the computational overhead and cost increase significantly

Engineering Contradiction:

Improveclock recovery accuracyVSAvoidcomputational complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The system replaces complex, expensive clock recovery apparatus with a simple averaging filter that computes the average PCR inter-arrival time. This simplified approach uses basic arithmetic operations instead of complex algorithms, significantly reducing computational overhead and cost while maintaining adequate clock recovery accuracy for practical applications.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The system changes the approach from complex real-time clock recovery algorithms to a simpler method based on averaging PCR arrival time differences. By transforming the problem into computing average inter-arrival times and using this statistic for clock adjustment, the system achieves acceptable accuracy with minimal computational complexity.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If PCR packet arrival is delayed due to channel conditions, then synchronization degradation occurs (color loss, jittery video, audio dropouts), but increasing processing power to handle delays increases system cost

Engineering Contradiction:

Improvesynchronization stabilityVSAvoidcomputational energy

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7489742B2System and method for clock recovery in digital video communication

Publication Date: 2009.02.10 STMICROELECTRONICS PVT LTD

AI summary

A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs. The controlled clock period difference computation element is coupled at its output to the error correction device to form a feedback circuit to minimize error between the system clock output and successive PCR differences.