Clock Recovery Loop With Pattern Error Correction for PDUI Distortion
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Solution Overview
Problem
Conventional clock and data recovery (CDR) systems are intolerant to deterministic distortion, particularly pattern-based distortions like Periodically Distorted Unit Interval (PDUI), which affects the accuracy of clock signal recovery and data sampling.
Innovation Solution
A system comprising a phase detector, filters, a controlled oscillator, and a pattern error detector that generates control signals to adjust the clock signal independently of transition density, allowing for the recovery of a clock signal that accurately samples data despite deterministic distortion, using a controlled oscillator circuit with an adder and accumulator to adjust the center frequency based on pattern errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR systems are used, then the system is simple and easy to operate, but the system is intolerant to deterministic distortion such as PDUI
Solution Approach 1:
The CDR system is segmented into two independent loops: a conventional phase detector loop for handling non-deterministic distortion (jitter) and a new pattern error detector loop for handling deterministic distortion (PDUI). Each loop processes specific types of distortion independently, allowing the system to address multiple distortion types without requiring a complete redesign of the entire CDR architecture.
Solution Approach 2:
A pattern error detector is introduced as an intermediary component between the phase detector and the controlled oscillator. This intermediary detects pattern-based deterministic distortion that the conventional phase detector misses, generates pattern error signals, and feeds them to the controlled oscillator for correction, thereby bridging the gap between simple conventional CDR and distortion-tolerant CDR.
2Measurement precision
If the clock signal recovery is dependent on transition density, then the system operation is straightforward, but the sampling accuracy deteriorates under deterministic distortion
Solution Approach 1:
The system implements feedback through the pattern error detector that continuously monitors the input signal for deterministic distortion patterns. The pattern error signals generated are fed back to the controlled oscillator, which adjusts the clock signal edges based on detected patterns, creating a closed-loop system that maintains sampling accuracy despite deterministic distortion.
Solution Approach 2:
The controlled oscillator dynamically changes the timing parameters of the recovered clock signal based on pattern error detection. When deterministic distortion is detected, the oscillator adjusts the clock edge positions to compensate for the distortion, thereby maintaining optimal sampling points without requiring complex operational changes throughout the system.
Data Source
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AI summary
A system can include a phase detector (105) configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter (110) coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector (120) configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter (125) coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator (115) coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal.