Clock Recovery Circuit With Dynamic Phase Alignment for CID Resistance
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Solution Overview
Problem
Existing clock data recovering apparatuses face challenges in maintaining accurate clock recovery due to poor consecutive identical digits (CID) resistance, especially when the frequency of the recovered clock does not match the bit rate of the input signal, leading to phase differences and data recovery failures during long signal level changes.
Innovation Solution
A clock generating apparatus with a signal selection unit, phase delay unit, time measurement unit, phase selection unit, phase detection unit, and phase control unit is employed, which selectively outputs edge signals and feedback clocks to adjust phase differences, using a cascade of delay elements and time measurement to optimize clock frequency and phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a clock data recovering apparatus operates in burst mode without external reference clock to reduce circuit scale and manufacturing cost, then circuit complexity and cost are reduced, but the frequency of recovered clock may not match the bit rate of input signal, causing phase difference accumulation and poor CID resistance
Solution Approach 1:
The patent implements dynamic frequency adjustment by measuring the actual bit rate of the input signal and adjusting the recovered clock frequency accordingly. The frequency adjustment unit dynamically modifies the clock frequency based on the measured bit rate, enabling the system to adapt to varying signal conditions and maintain accurate synchronization without requiring external reference clocks, thus resolving the contradiction between circuit simplicity and reliable operation.
Solution Approach 2:
The system changes the frequency parameter of the recovered clock based on measured bit rate variations. By continuously monitoring the input signal characteristics and adjusting the clock frequency parameter in response, the system maintains synchronization accuracy under different operating conditions, improving CID resistance while keeping the circuit design simple and self-contained.
2Device complexity
If the frequency of recovered clock is fixed without dynamic adjustment, then circuit complexity is reduced, but phase difference accumulates during long signal level changes, leading to data recovery failure
Solution Approach 1:
The patent implements a feedback mechanism where the actual bit rate of the input signal is measured and used to adjust the recovered clock frequency. The frequency adjustment unit receives feedback about signal characteristics and modifies the clock frequency accordingly, creating a closed-loop system that maintains phase alignment accuracy without requiring complex predetermined calibration circuits.
Solution Approach 2:
The system performs self-adjustment by automatically measuring its own operating conditions (input signal bit rate) and correcting its own output (recovered clock frequency). This self-service capability eliminates the need for external reference clocks or complex pre-calibration circuits, maintaining high phase alignment accuracy while keeping the overall circuit design simple.
Data Source
AI summary
This embodiment relates to a clock data recovering apparatus capable of improving consecutive identical digits (CID) resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.