Optical Transport Clock Recovery with Clipped Phase Accumulation

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Solution Overview

Problem

Existing optical transport networks face challenges in ensuring that the service clock recovered by the transport network is highly consistent with the service clock received by the client device, leading to potential inaccuracies and reduced system reliability.

Innovation Solution

A method for clock recovery in optical transport networks that involves obtaining and accumulating phase difference information across multiple devices, using a nonlinear signal processing mechanism to generate target phase difference information, which is clipped to specific values (first value, second value, or 0) to reduce jitter and improve accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If phase difference information is accumulated through multiple upstream devices, then clock recovery accuracy is improved, but jitter increases due to quantization accumulation

Engineering Contradiction:
Improveclock recovery accuracyVSAvoidjitter
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by performing clipping of the accumulated phase difference information before it is used for clock recovery. The destination device clips the accumulated phase difference to a predetermined range (e.g., -π to π) before feeding it into the clock recovery algorithm. This preliminary clipping prevents the accumulation of quantization errors and jitter that would otherwise occur through multiple devices, while still maintaining the benefits of accumulated phase difference information for improved clock recovery accuracy.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If target phase difference information is clipped to specific values, then jitter is reduced and system reliability is improved, but some phase difference information may be lost

Engineering Contradiction:
Improvesystem reliabilityVSAvoidphase difference information
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent applies parameter changes by transforming the accumulated phase difference information through clipping to a predetermined range. This changes the parameter distribution of the phase difference information, concentrating it within a reliable range that prevents jitter accumulation. The clipping operation modifies the parameter values to ensure system reliability, and the patent compensates for any information loss by using the clipped values in a feedback mechanism that continuously refines the clock recovery process.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If accumulated phase difference information is used for clock recovery, then lossless clock recovery is implemented, but complexity of the recovery process increases

Engineering Contradiction:
Improveclock recovery integrityVSAvoidrecovery process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies feedback by using the clipped accumulated phase difference information in a closed-loop clock recovery process. The destination device continuously monitors the recovered clock quality and adjusts the clipping range and accumulation process accordingly. This feedback mechanism ensures lossless clock recovery by continuously optimizing the parameters, while the automated nature of the feedback loop prevents excessive manual complexity in the recovery process.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20260039407A1Clock recovery method, apparatus, and system
Publication Date: 2026.02.05 HUAWEI TECH CO LTD
  • US20260039407A1 patent drawing
  • US20260039407A1 patent drawing
  • US20260039407A1 patent drawing

AI summary

A clock recovery method, an apparatus, and a system are provided in which first phase difference information is obtained, and target phase difference information is generated based on the first phase difference information and accumulated phase difference information. A clock of a first data frame can be recovered based on the target phase difference information. The first phase difference information is a sum of input phase difference information and a local phase difference. The input phase difference information is a sum of phase differences between one or more groups of two adjacent upstream devices in one or more upstream devices of a destination device through which the first data frame passes. The accumulated phase difference information is an accumulation of differences between historical first phase difference information and historical target phase difference information that are present before a destination device obtains the first phase difference information.