Clock Recovery Circuit Using Local Phase-Multiplied Clocks
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Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits face challenges in designing low jitter CMOS circuits with high-frequency PLL/VCOs, leading to increased power consumption and mismatching effects in high-speed data communication systems, especially as data rates increase, due to the need for multiple PLLs and complex clock signal transmission.
Innovation Solution
A circuit that employs a frequency multiplier to generate local clock signals with different phases from a global clock signal, a phase interpolator to generate a recovered clock signal, and a phase shifter to synchronize the clock signal with input data, reducing the need for high-frequency PLL/VCOs and minimizing power consumption and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single PLL is used to generate high-frequency clock signals for high-speed data communication, then device complexity is reduced, but jitter characteristics and power consumption worsen
Solution Approach 1:
The clock signal generation is segmented into two stages: a first PLL generates a lower-frequency clock signal with good jitter characteristics, then a frequency multiplier circuit (comprising phase interpolators and XOR gates) multiplies the frequency to achieve the required high data rate. This segmentation allows the PLL to operate at a manageable frequency while still supporting high-speed data communication.
Solution Approach 2:
A frequency multiplier circuit acts as an intermediary between the PLL and the high-speed data channels. This intermediary circuit multiplies the clock frequency without requiring the PLL itself to operate at the high frequency, thus maintaining low jitter while achieving high data rates.
2Area of stationary object
If a single PLL is used to generate high-frequency clock signals, then chip area is reduced, but power consumption increases
Solution Approach 1:
The power-consuming frequency multiplication function is segmented from the PLL and implemented using combinational logic circuits (phase interpolators and XOR gates). These circuits consume less power than running the PLL at high frequency, thus reducing overall power consumption while maintaining a single PLL structure for compact chip area.
3Reliability
If multiple PLLs are used to generate clock signals, then jitter characteristics improve, but device complexity and chip area increase
Solution Approach 1:
Multiple clock signal generation functions are merged into a single PLL output. The first PLL generates one clock signal that is then distributed to multiple phase interpolators, which collectively provide the clock signals for multiple channels. This merging approach maintains low jitter characteristics while reducing device complexity and chip area compared to using multiple separate PLLs.
4Productivity
If high-frequency clock signals are transmitted to multiple channels, then data rate increases, but mismatching and coupling effects increase
Solution Approach 1:
Instead of transmitting high-frequency clock signals from a central PLL to multiple channels (which causes mismatching and coupling), the approach is inverted: a single channel generates the high-frequency clock locally using a frequency multiplier, and this clock is then used for data recovery in other channels. This inversion eliminates the harmful transmission effects while maintaining high data rates.
Data Source
AI summary
A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a different phase. The local clock signals may be generated at a second frequency higher than the first frequency. The circuit may include a phase interpolator configured to generate a recovered clock signal at a given phase and at a third frequency, based on the generated local clock signals, and a phase shifter configured to adjust the phase of the recovered clock signal so as to synchronize the phase of the recovered clock signal with a phrase of input data that is input to the phase shifter.