Clock Data Recovery Circuit With Phase Combining for Stable Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Clock data recovery circuits face challenges in maintaining accurate frequency detection and signal recovery due to variations in operating temperature and power supply voltage, which affect the phase difference between clock signals, leading to reduced performance and increased circuit size and power consumption.
Innovation Solution
A clock data recovery circuit that includes a phase detector circuit, a clock signal generation circuit, a phase combining circuit, and a recovered data generation circuit, where the phase difference between the first and second clock signals is maintained at 90 degrees, using a variable delay circuit or phase combining circuit to adjust the phase of the recovered clock signal, ensuring optimal sampling and minimizing the impact of temperature and power supply voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the phase difference between clock signals is adjusted to maintain frequency detection accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces a phase combining circuit as an intermediary component that receives multiple clock signals with different phases and synthesizes them into a recovered clock signal. This mediator structure enables accurate frequency detection by combining phase information from multiple sources without requiring direct complex adjustment between individual clock signals, thus improving measurement precision while managing device complexity through functional decomposition
Solution Approach 2:
The clock signal generation is segmented into multiple independent clock signals with specific phase relationships (first clock signal and second clock signal with less than 180° phase difference). The phase combining circuit then processes these segmented signals separately before combining them, allowing for simplified individual signal processing and maintaining overall system accuracy without excessive complexity
2Reliability
If temperature and power supply voltage variations are compensated to maintain phase difference, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent employs variable delay circuits that can dynamically adjust their delay characteristics in response to temperature and power supply voltage variations. By changing the delay parameter adaptively, the system maintains the required phase relationship between clock signals under varying environmental conditions, improving reliability without requiring complex compensation mechanisms
Solution Approach 2:
The phase combining circuit continuously processes clock signals and generates a recovered clock signal that reflects the combined phase information. This creates a feedback mechanism where the system can detect phase deviations caused by environmental variations and adjust accordingly, maintaining signal recovery performance while using a relatively simple circuit structure
3Measurement precision
If multiple clock signals are combined to improve frequency detection, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent merges multiple clock signals with different phases into a single recovered clock signal through the phase combining circuit. By combining these signals constructively, the system achieves improved frequency detection accuracy while processing them through a unified circuit path, thereby reducing overall power consumption compared to processing multiple independent high-precision clock circuits separately
Data Source
AI summary
A clock data recovery circuit includes: a phase detector circuit configured to generate a phase detection signal indicating a first detection result between a phase of a reception data signal and a phase of a first clock signal; a clock signal generation circuit configured to generate the first clock signal and a second clock signal based on the phase detection signal, the second clock signal having a frequency substantially equal to a frequency of the first clock signal, a phase difference between the first clock signal and the second clock signal being less than 180°; a phase combining circuit configured to combine the first clock signal and the second clock signal in accordance with a phase relation and generate a recovered clock signal; and a recovered data generation circuit configured to sample the reception data signal and generate a recovered data signal based on the recovered clock signal.